Marek Behún 239f424f49 clk: armada-37xx-periph: fix DDR PHY clock divider values ...

Register value table for DDR PHY clock divider are wrong. They should be
0 or 1 for divide-by-2 or divide-by-4, respectively. Not 1 or 2. Current
values do not make sense, since 2 cannot be achieved, because the
register is only 1 bit long (mask is set to 1).

This fixes clk dump reporting DDR PHY clock rate differently from Linux.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>

2020-04-22 14:28:15 +02:00

..

armada-37xx-periph.c

clk: armada-37xx-periph: fix DDR PHY clock divider values

2020-04-22 14:28:15 +02:00

armada-37xx-tbg.c

dm: core: Create a new header file for 'compat' features

2020-02-05 19:33:46 -07:00

Kconfig

driver: clk: Add support for clocks on Armada 37xx

2018-05-14 10:00:15 +02:00

Makefile

driver: clk: Add support for clocks on Armada 37xx

2018-05-14 10:00:15 +02:00