Andre Przywara a94c9c809b sunxi: clock: support D1/R528 PLL6 clock ...

The PLL_PERIPH0 clock changed a bit in the D1/R528/T113s SoCs: there is
new P0 divider at bits [18:16], and the M divider is 1.

Add code to support this version of "PLL6".

Signed-off-by: Andre Przywara <andre.przywara@arm.com>

2023-10-22 23:41:51 +01:00

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arc

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arm

sunxi: clock: support D1/R528 PLL6 clock

2023-10-22 23:41:51 +01:00

m68k

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microblaze

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mips

spl: Use SYS_MALLOC_F instead of SYS_MALLOC_F_LEN

2023-10-06 14:38:12 -04:00

nios2

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powerpc

spl: Use SYS_MALLOC_F instead of SYS_MALLOC_F_LEN

2023-10-06 14:38:12 -04:00

riscv

sunxi: dts: arm: add T113s/D1 DT files from Linux-v6.6-rc6

2023-10-22 01:12:26 +01:00

sandbox

sandbox: watchdog: Avoid an error on startup

2023-10-19 07:50:18 +02:00

sh

spl: Use SYS_MALLOC_F instead of SYS_MALLOC_F_LEN

2023-10-06 14:38:12 -04:00

x86

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xtensa

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.gitignore

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Kconfig

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Kconfig.nxp

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u-boot-elf.lds

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