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80b529d877
Enable cache for J722s to optimize performance of CPU to access data from memory. Reviewed-by: Alexander Sverdlin <alexander.sverdlin@siemens.com> Signed-off-by: Chintan Vankar <c-vankar@ti.com>
45 lines
861 B
C
45 lines
861 B
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Board specific initialization for J722S platforms
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*
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* Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
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*
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*/
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#include <asm/arch/hardware.h>
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#include <asm/io.h>
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#include <cpu_func.h>
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#include <dm/uclass.h>
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#include <env.h>
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#include <fdt_support.h>
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#include <spl.h>
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#include <asm/arch/k3-ddr.h>
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#include "../common/fdt_ops.h"
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#if IS_ENABLED(CONFIG_SPL_BUILD)
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void spl_board_init(void)
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{
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enable_caches();
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}
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#endif
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#if defined(CONFIG_XPL_BUILD)
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void spl_perform_fixups(struct spl_image_info *spl_image)
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{
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if (IS_ENABLED(CONFIG_K3_DDRSS)) {
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if (IS_ENABLED(CONFIG_K3_INLINE_ECC))
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fixup_ddr_driver_for_ecc(spl_image);
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} else {
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fixup_memory_node(spl_image);
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}
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}
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#endif
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#if IS_ENABLED(CONFIG_BOARD_LATE_INIT)
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int board_late_init(void)
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{
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ti_set_fdt_env(NULL, NULL);
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return 0;
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}
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#endif
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