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87 lines
1.8 KiB
C
87 lines
1.8 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2025 Svyatoslav Ryhel <clamor95@gmail.com>
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*/
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#include <dm.h>
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#include <clk.h>
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#include <log.h>
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#include <reset.h>
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#include <linux/delay.h>
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#include <asm/arch/clock.h>
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#include <asm/arch-tegra/clk_rst.h>
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struct tegra_host1x_info {
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u32 clk_parent;
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u32 rate;
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};
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static int tegra_host1x_probe(struct udevice *dev)
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{
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struct clk *clk;
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struct reset_ctl reset_ctl;
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const struct tegra_host1x_info *info;
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int ret;
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clk = devm_clk_get(dev, NULL);
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if (IS_ERR(clk)) {
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log_debug("%s: cannot get HOST1X clock: %ld\n",
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__func__, PTR_ERR(clk));
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return PTR_ERR(clk);
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}
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ret = reset_get_by_name(dev, "host1x", &reset_ctl);
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if (ret) {
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log_debug("%s: cannot get HOST1X reset: %d\n",
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__func__, ret);
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return ret;
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}
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info = (struct tegra_host1x_info *)dev_get_driver_data(dev);
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reset_assert(&reset_ctl);
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clock_start_periph_pll(clk->id, info->clk_parent, info->rate);
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mdelay(2);
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reset_deassert(&reset_ctl);
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return 0;
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}
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static const struct tegra_host1x_info tegra20_host1x_info = {
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.clk_parent = CLOCK_ID_CGENERAL,
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.rate = 150000000, /* 150 MHz */
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};
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static const struct tegra_host1x_info tegra114_host1x_info = {
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.clk_parent = CLOCK_ID_PERIPH,
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.rate = 136000000, /* 136 MHz */
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};
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static const struct udevice_id tegra_host1x_ids[] = {
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{
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.compatible = "nvidia,tegra20-host1x",
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.data = (ulong)&tegra20_host1x_info
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}, {
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.compatible = "nvidia,tegra30-host1x",
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.data = (ulong)&tegra20_host1x_info
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}, {
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.compatible = "nvidia,tegra114-host1x",
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.data = (ulong)&tegra114_host1x_info
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}, {
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.compatible = "nvidia,tegra124-host1x",
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.data = (ulong)&tegra114_host1x_info
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}, {
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/* sentinel */
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}
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};
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U_BOOT_DRIVER(tegra_host1x) = {
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.name = "tegra_host1x",
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.id = UCLASS_SIMPLE_BUS,
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.of_match = tegra_host1x_ids,
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.probe = tegra_host1x_probe,
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.flags = DM_FLAG_PRE_RELOC,
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};
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