Files
u-boot/arch
Xingyu Wu 6c4b50e6de riscv: dts: jh7110: Add clock source from PLL
Change the PLL clock source from syscrg to sys_syscon child node.

Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Reviewed-by: Torsten Duwe <duwe@suse.de>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-07-24 13:21:06 +08:00
..
2023-05-31 14:05:34 -04:00
2023-07-20 14:10:57 -06:00
2023-05-31 14:05:34 -04:00
2023-05-11 10:25:29 +08:00