Bin Meng 49191d259f clk: sifive: Add clock driver for GEMGXL MGMT ...

This adds a clock driver to support the GEMGXL management IP block
found in FU540 SoCs to control GEM TX clock operation mode for
10/100/1000 Mbps.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Tested-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>

2019-06-01 13:33:17 -05:00

..

analogbits-wrpll-cln28hpc.h

clk: Add SiFive FU540 PRCI clock driver

2019-02-27 09:12:33 +08:00

fu540-prci.c

clk: sifive: fu540-prci: Change include order

2019-05-09 00:43:59 +05:30

gemgxl-mgmt.c

clk: sifive: Add clock driver for GEMGXL MGMT

2019-06-01 13:33:17 -05:00

Kconfig

clk: sifive: Add clock driver for GEMGXL MGMT

2019-06-01 13:33:17 -05:00

Makefile

clk: sifive: Add clock driver for GEMGXL MGMT

2019-06-01 13:33:17 -05:00

wrpll-cln28hpc.c

clk: Add SiFive FU540 PRCI clock driver

2019-02-27 09:12:33 +08:00