Takahiro Kuwano a4aa9b7522 mtd: spi-nor-core: Add support for volatile QE bit ...

Some of Spansion/Cypress chips support volatile version of configuration
registers and it is recommended to update volatile registers in the field
application due to a risk of the non-volatile registers corruption by
power interrupt. This patch adds a function to set Quad Enable bit in CFR1
volatile.

Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>

2021-06-29 19:16:54 +05:30

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bbm.h

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cfi.h

mtd: spi: Port SPI NOR framework from Linux

2019-02-07 15:33:21 +05:30

concat.h

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doc2000.h

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flashchip.h

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fsl_upm.h

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fsmc_nand.h

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mtd.h

mtd: add support for parsing partitions defined in OF

2021-06-24 11:53:15 +05:30

nand_bch.h

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nand_ecc.h

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nand.h

spi: Tidy up get/set of device node

2021-01-05 12:24:41 -07:00

ndfc.h

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omap_elm.h

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omap_gpmc.h

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onenand_regs.h

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onenand.h

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partitions.h

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rawnand.h

arm: Don't include common.h in header files

2020-05-18 14:54:24 -04:00

samsung_onenand.h

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spi-nor.h

mtd: spi-nor-core: Add support for volatile QE bit

2021-06-29 19:16:54 +05:30

spinand.h

spi: Tidy up get/set of device node

2021-01-05 12:24:41 -07:00

st_smi.h

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ubi.h

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