Kumar Gala a880cf3e0e ppc/p4080: CoreNet platfrom style CCSRBAR setting ...

On CoreNet based platforms the CCSRBAR address is split between an high &
low register and we no longer shift the address.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Scott Wood <scottwood@freescale.com>

2009-09-24 12:05:28 -05:00

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74xx_7xx

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arm720t

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arm920t

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arm926ejs

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arm946es

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arm1136

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arm1176

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arm_cortexa8

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arm_intcm

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at32ap

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blackfin

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i386

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ixp

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leon2

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leon3

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lh7a40x

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mcf52x2

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mcf523x

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microblaze

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mips

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mpc5xx

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mpc5xxx

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mpc8xx

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mpc8xxx

ppc/8xxx: Misc DDR related fixes

2009-09-15 21:30:08 -05:00

mpc83xx

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mpc85xx

ppc/p4080: CoreNet platfrom style CCSRBAR setting

2009-09-24 12:05:28 -05:00

mpc86xx

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mpc512x

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mpc824x

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mpc8220

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mpc8260

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nios

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nios2

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ppc4xx

ppc4xx: Fix PCIE PLL lock on 440SPe Yucca board

2009-09-23 15:46:08 +02:00

pxa

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s3c44b0

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sa1100

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sh2

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