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aa6e94deab
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
186 lines
3.8 KiB
C
186 lines
3.8 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2005-2009
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* BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de>
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*
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* (C) Copyright 2000-2003
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*/
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#include <common.h>
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#include <command.h>
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#include <asm/global_data.h>
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#include "asm/m5282.h"
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#include <bmp_layout.h>
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#include <env.h>
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#include <init.h>
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#include <status_led.h>
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#include <bus_vcxk.h>
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/*---------------------------------------------------------------------------*/
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DECLARE_GLOBAL_DATA_PTR;
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/*---------------------------------------------------------------------------*/
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int checkboard (void)
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{
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puts("Board: EB+CPU5282 (BuS Elektronik GmbH & Co. KG)\n");
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#if (CONFIG_TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE)
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puts(" Boot from Internal FLASH\n");
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#endif
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return 0;
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}
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int dram_init(void)
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{
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int size, i;
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size = 0;
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MCFSDRAMC_DCR = MCFSDRAMC_DCR_RTIM_6 |
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MCFSDRAMC_DCR_RC((15 * CONFIG_SYS_CLK / 1000000) >> 4);
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asm (" nop");
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#ifdef CFG_SYS_SDRAM_BASE0
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MCFSDRAMC_DACR0 = MCFSDRAMC_DACR_BASE(CFG_SYS_SDRAM_BASE0)|
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MCFSDRAMC_DACR_CASL(1) | MCFSDRAMC_DACR_CBM(3) |
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MCFSDRAMC_DACR_PS_32;
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asm (" nop");
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MCFSDRAMC_DMR0 = MCFSDRAMC_DMR_BAM_16M | MCFSDRAMC_DMR_V;
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asm (" nop");
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MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_IP;
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asm (" nop");
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for (i = 0; i < 10; i++)
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asm (" nop");
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*(unsigned long *)(CFG_SYS_SDRAM_BASE0) = 0xA5A5A5A5;
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asm (" nop");
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MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_RE;
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asm (" nop");
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for (i = 0; i < 2000; i++)
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asm (" nop");
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MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_IMRS;
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asm (" nop");
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/* write SDRAM mode register */
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*(unsigned long *)(CFG_SYS_SDRAM_BASE0 + 0x80440) = 0xA5A5A5A5;
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asm (" nop");
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size += CFG_SYS_SDRAM_SIZE0 * 1024 * 1024;
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#endif
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#ifdef CFG_SYS_SDRAM_BASE1xx
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MCFSDRAMC_DACR1 = MCFSDRAMC_DACR_BASE (CFG_SYS_SDRAM_BASE1)
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| MCFSDRAMC_DACR_CASL (1)
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| MCFSDRAMC_DACR_CBM (3)
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| MCFSDRAMC_DACR_PS_16;
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MCFSDRAMC_DMR1 = MCFSDRAMC_DMR_BAM_16M | MCFSDRAMC_DMR_V;
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MCFSDRAMC_DACR1 |= MCFSDRAMC_DACR_IP;
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*(unsigned short *) (CFG_SYS_SDRAM_BASE1) = 0xA5A5;
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MCFSDRAMC_DACR1 |= MCFSDRAMC_DACR_RE;
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for (i = 0; i < 2000; i++)
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asm (" nop");
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MCFSDRAMC_DACR1 |= MCFSDRAMC_DACR_IMRS;
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*(unsigned int *) (CFG_SYS_SDRAM_BASE1 + 0x220) = 0xA5A5;
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size += CFG_SYS_SDRAM_SIZE1 * 1024 * 1024;
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#endif
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gd->ram_size = size;
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return 0;
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}
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#if defined(CONFIG_SYS_DRAM_TEST)
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int testdram(void)
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{
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uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
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uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
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uint *p;
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printf("SDRAM test phase 1:\n");
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for (p = pstart; p < pend; p++)
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*p = 0xaaaaaaaa;
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for (p = pstart; p < pend; p++) {
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if (*p != 0xaaaaaaaa) {
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printf ("SDRAM test fails at: %08x\n", (uint) p);
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return 1;
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}
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}
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printf("SDRAM test phase 2:\n");
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for (p = pstart; p < pend; p++)
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*p = 0x55555555;
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for (p = pstart; p < pend; p++) {
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if (*p != 0x55555555) {
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printf ("SDRAM test fails at: %08x\n", (uint) p);
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return 1;
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}
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}
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printf("SDRAM test passed.\n");
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return 0;
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}
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#endif
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#if defined(CONFIG_HW_WATCHDOG)
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void hw_watchdog_init(void)
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{
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char *s;
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int enable;
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enable = 1;
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s = env_get("watchdog");
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if (s != NULL)
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if ((strncmp(s, "off", 3) == 0) || (strncmp(s, "0", 1) == 0))
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enable = 0;
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if (enable)
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MCFGPTA_GPTDDR |= (1<<2);
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else
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MCFGPTA_GPTDDR &= ~(1<<2);
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}
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void hw_watchdog_reset(void)
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{
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MCFGPTA_GPTPORT ^= (1<<2);
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}
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#endif
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int misc_init_r(void)
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{
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#ifdef CONFIG_HW_WATCHDOG
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hw_watchdog_init();
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#endif
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return 1;
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}
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void __led_toggle(led_id_t mask)
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{
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MCFGPTA_GPTPORT ^= (1 << 3);
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}
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void __led_init(led_id_t mask, int state)
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{
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__led_set(mask, state);
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MCFGPTA_GPTDDR |= (1 << 3);
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}
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void __led_set(led_id_t mask, int state)
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{
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if (state == CONFIG_LED_STATUS_ON)
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MCFGPTA_GPTPORT |= (1 << 3);
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else
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MCFGPTA_GPTPORT &= ~(1 << 3);
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}
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/*---------------------------------------------------------------------------*/
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/* EOF EB+MCF-EV123.c */
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