mirror of
https://source.denx.de/u-boot/u-boot.git
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17d80a3b32
Supports both GXBB and GXL SoCs. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Ferass El Hafidi <funderscore@postmarketos.org> Link: https://patch.msgid.link/20251126-spl-gx-v5-5-6cbffb2451ca@postmarketos.org Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
342 lines
11 KiB
C
342 lines
11 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2015, Amlogic, Inc. All rights reserved.
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* Copyright (C) 2023, Ferass El Hafidi <funderscore@postmarketos.org>
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*/
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#ifndef DRAM_GX_H
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#define DRAM_GX_H
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/*
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* Registers
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*/
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/* PCTL */
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#define DDR0_PCTL_BASE 0xc8839000
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/* DDR1_PCTL_BASE is DDR0_PCTL_BASE + 0x400 */
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/* DMC */
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#define DMC_REG_BASE 0xc8838000
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#define DMC_REQ_CTRL (DMC_REG_BASE + (0x00 << 2))
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#define DMC_SOFT_RST (DMC_REG_BASE + (0x01 << 2))
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#define DMC_SOFT_RST1 (DMC_REG_BASE + (0x02 << 2))
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#define DMC_RST_STS (DMC_REG_BASE + (0x03 << 2))
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#define DMC_VERSION (DMC_REG_BASE + (0x05 << 2))
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#define DMC_REFR_CTRL1 (DMC_REG_BASE + (0x23 << 2))
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#define DMC_REFR_CTRL2 (DMC_REG_BASE + (0x24 << 2))
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#define DMC_PCTL_LP_CTRL (DMC_REG_BASE + (0x46 << 2))
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#define DMC_AM0_QOS_INC (DMC_REG_BASE + (0x62 << 2))
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#define DMC_AM0_QOS_DEC (DMC_REG_BASE + (0x64 << 2))
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#define DMC_AM0_QOS_DIS (DMC_REG_BASE + (0x66 << 2))
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#define DMC_AM1_QOS_INC (DMC_REG_BASE + (0x6c << 2))
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#define DMC_AM1_QOS_DEC (DMC_REG_BASE + (0x6e << 2))
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#define DMC_AM1_QOS_DIS (DMC_REG_BASE + (0x70 << 2))
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#define DMC_AM2_QOS_INC (DMC_REG_BASE + (0x76 << 2))
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#define DMC_AM2_QOS_DEC (DMC_REG_BASE + (0x78 << 2))
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#define DMC_AM2_QOS_DIS (DMC_REG_BASE + (0x7a << 2))
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#define DMC_AM3_QOS_INC (DMC_REG_BASE + (0x80 << 2))
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#define DMC_AM3_QOS_DEC (DMC_REG_BASE + (0x82 << 2))
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#define DMC_AM3_QOS_DIS (DMC_REG_BASE + (0x84 << 2))
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#define DMC_AM4_QOS_INC (DMC_REG_BASE + (0x8a << 2))
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#define DMC_AM4_QOS_DEC (DMC_REG_BASE + (0x8c << 2))
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#define DMC_AM4_QOS_DIS (DMC_REG_BASE + (0x8e << 2))
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#define DMC_AM5_QOS_INC (DMC_REG_BASE + (0x94 << 2))
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#define DMC_AM5_QOS_DEC (DMC_REG_BASE + (0x96 << 2))
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#define DMC_AM5_QOS_DIS (DMC_REG_BASE + (0x98 << 2))
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#define DMC_AM6_QOS_INC (DMC_REG_BASE + (0x9e << 2))
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#define DMC_AM6_QOS_DEC (DMC_REG_BASE + (0xa0 << 2))
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#define DMC_AM6_QOS_DIS (DMC_REG_BASE + (0xa2 << 2))
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#define DMC_AM7_QOS_INC (DMC_REG_BASE + (0xa8 << 2))
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#define DMC_AM7_QOS_DEC (DMC_REG_BASE + (0xaa << 2))
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#define DMC_AM7_QOS_DIS (DMC_REG_BASE + (0xac << 2))
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#define DMC_AXI0_QOS_INC (DMC_REG_BASE + (0xb2 << 2))
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#define DMC_AXI0_QOS_DEC (DMC_REG_BASE + (0xb4 << 2))
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#define DMC_AXI0_QOS_DIS (DMC_REG_BASE + (0xb6 << 2))
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#define DMC_AXI0_QOS_CTRL1 (DMC_REG_BASE + (0xb9 << 2))
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#define DMC_AXI1_QOS_INC (DMC_REG_BASE + (0xbc << 2))
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#define DMC_AXI1_QOS_DEC (DMC_REG_BASE + (0xbe << 2))
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#define DMC_AXI1_QOS_DIS (DMC_REG_BASE + (0xc0 << 2))
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#define DMC_AXI2_QOS_INC (DMC_REG_BASE + (0xc6 << 2))
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#define DMC_AXI2_QOS_DEC (DMC_REG_BASE + (0xc8 << 2))
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#define DMC_AXI2_QOS_DIS (DMC_REG_BASE + (0xca << 2))
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#define DMC_AXI3_QOS_INC (DMC_REG_BASE + (0xd0 << 2))
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#define DMC_AXI3_QOS_DEC (DMC_REG_BASE + (0xd2 << 2))
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#define DMC_AXI3_QOS_DIS (DMC_REG_BASE + (0xd4 << 2))
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#define DMC_AXI4_QOS_INC (DMC_REG_BASE + (0xda << 2))
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#define DMC_AXI4_QOS_DEC (DMC_REG_BASE + (0xdc << 2))
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#define DMC_AXI4_QOS_DIS (DMC_REG_BASE + (0xde << 2))
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#define DMC_AXI5_QOS_INC (DMC_REG_BASE + (0xe4 << 2))
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#define DMC_AXI5_QOS_DEC (DMC_REG_BASE + (0xe6 << 2))
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#define DMC_AXI5_QOS_DIS (DMC_REG_BASE + (0xe8 << 2))
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#define DMC_AXI6_QOS_INC (DMC_REG_BASE + (0xee << 2))
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#define DMC_AXI6_QOS_DEC (DMC_REG_BASE + (0xf0 << 2))
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#define DMC_AXI6_QOS_DIS (DMC_REG_BASE + (0xf2 << 2))
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#define DMC_AXI7_QOS_INC (DMC_REG_BASE + (0xf8 << 2))
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#define DMC_AXI7_QOS_DEC (DMC_REG_BASE + (0xfa << 2))
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#define DMC_AXI7_QOS_DIS (DMC_REG_BASE + (0xfc << 2))
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/* DDR MMC */
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#define AM_DDR_PLL_CNTL0 (DDR_MMC_BASE + 0x00)
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#define AM_DDR_PLL_CNTL1 (DDR_MMC_BASE + 0x04)
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#define AM_DDR_PLL_CNTL2 (DDR_MMC_BASE + 0x08)
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#define AM_DDR_PLL_CNTL3 (DDR_MMC_BASE + 0x0c)
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#define AM_DDR_PLL_CNTL4 (DDR_MMC_BASE + 0x10)
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#if defined(CONFIG_MESON_GXBB)
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#define AM_DDR_PLL_STS (DDR_MMC_BASE + 0x14)
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#else
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#define AM_DDR_PLL_CNTL5 (DDR_MMC_BASE + 0x14)
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#endif
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#define DDR0_CLK_CTRL (DDR_MMC_BASE + 0x400)
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/* DMC SEC */
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#define DMC_SEC_REG_BASE 0xda838400
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#define DMC_SEC_CTRL (DMC_SEC_REG_BASE + (0x00 << 2))
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#define DMC_SEC_RANGE_CTRL (DMC_SEC_REG_BASE + (0x07 << 2))
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#define DMC_SEC_AXI_PORT_CTRL (DMC_SEC_REG_BASE + (0x0e << 2))
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#define DMC_VDEC_SEC_READ_CTRL (DMC_SEC_REG_BASE + (0x10 << 2))
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#define DMC_VDEC_SEC_WRITE_CTRL (DMC_SEC_REG_BASE + (0x11 << 2))
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#define DMC_VDEC_SEC_CFG (DMC_SEC_REG_BASE + (0x12 << 2))
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#define DMC_HCODEC_SEC_READ_CTRL (DMC_SEC_REG_BASE + (0x17 << 2))
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#define DMC_HCODEC_SEC_WRITE_CTRL (DMC_SEC_REG_BASE + (0x18 << 2))
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#define DMC_HCODEC_SEC_CFG (DMC_SEC_REG_BASE + (0x19 << 2))
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#define DMC_HEVC_SEC_READ_CTRL (DMC_SEC_REG_BASE + (0x1e << 2))
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#define DMC_HEVC_SEC_WRITE_CTRL (DMC_SEC_REG_BASE + (0x1f << 2))
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#define DMC_HEVC_SEC_CFG (DMC_SEC_REG_BASE + (0x20 << 2))
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#define DMC_VPU_SEC_READ_CTRL (DMC_SEC_REG_BASE + (0x32 << 2))
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#define DMC_VPU_SEC_WRITE_CTRL (DMC_SEC_REG_BASE + (0x33 << 2))
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#define DMC_VPU_SEC_CFG (DMC_SEC_REG_BASE + (0x25 << 2))
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#define DMC_GE2D_SEC_CTRL (DMC_SEC_REG_BASE + (0x34 << 2))
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#define DMC_PARSER_SEC_CTRL (DMC_SEC_REG_BASE + (0x35 << 2))
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#define DMC_DEV_SEC_READ_CTRL (DMC_SEC_REG_BASE + (0x36 << 2))
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#define DMC_DEV_SEC_WRITE_CTRL (DMC_SEC_REG_BASE + (0x37 << 2))
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#define DMC_WTCH0_CTRL (DMC_SEC_REG_BASE + (0xa9 << 2))
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#define DMC_WTCH1_CTRL (DMC_SEC_REG_BASE + (0xb0 << 2))
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#define DDR0_ADDRMAP_0 (DMC_SEC_REG_BASE + (0xd0 << 2))
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#define DDR0_ADDRMAP_1 (DMC_SEC_REG_BASE + (0xd1 << 2))
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#define DDR0_ADDRMAP_2 (DMC_SEC_REG_BASE + (0xd2 << 2))
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#define DDR0_ADDRMAP_3 (DMC_SEC_REG_BASE + (0xd3 << 2))
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#define DDR0_ADDRMAP_4 (DMC_SEC_REG_BASE + (0xd4 << 2))
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#define DDR1_ADDRMAP_0 (DMC_SEC_REG_BASE + (0xd5 << 2))
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#define DDR1_ADDRMAP_1 (DMC_SEC_REG_BASE + (0xd6 << 2))
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#define DDR1_ADDRMAP_2 (DMC_SEC_REG_BASE + (0xd7 << 2))
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#define DDR1_ADDRMAP_3 (DMC_SEC_REG_BASE + (0xd8 << 2))
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#define DDR1_ADDRMAP_4 (DMC_SEC_REG_BASE + (0xd9 << 2))
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#if defined(CONFIG_MESON_GXL)
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#define DMC_DES_KEY0_H (DMC_SEC_REG_BASE + (0x90 << 2))
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#define DMC_DES_KEY0_L (DMC_SEC_REG_BASE + (0x91 << 2))
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#define DMC_DES_KEY1_H (DMC_SEC_REG_BASE + (0x92 << 2))
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#define DMC_DES_KEY1_L (DMC_SEC_REG_BASE + (0x93 << 2))
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#define DMC_DES_CTRL (DMC_SEC_REG_BASE + (0x9d << 2))
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#endif
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#define DMC_DDR_CTRL (DMC_SEC_REG_BASE + (0xda << 2))
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#define AM_ANALOG_TOP_REG1 (0xc8834400 + (0x6f << 2))
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/* Macros */
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#define DQSCORR_DX(dx) \
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if ((readl(dx) & ~(0xe00)) && ((readl(dx) >> 8) & ~(0xe00))) \
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writel((((readl(dx) & ~(0xe00)) * 95) / 100) | \
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(((((readl(dx) >> 8) & ~(0xe00)) * 88) / 100) << 8) | \
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(((((readl(dx) >> 8) & ~(0xe00)) * 88) / 100) << 16), \
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dx); \
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else if (((readl(dx) >> 8) & ~(0xe00))) \
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writel((95 / 100) | \
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(((((readl(dx) >> 8) & ~(0xe00)) * 88) / 100) << 8) | \
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(((((readl(dx) >> 8) & ~(0xe00)) * 88) / 100) << 16), \
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dx); \
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else if (((readl(dx)) & ~(0xe00))) \
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writel((((readl(dx) & ~(0xe00)) * 95) / 100) | \
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(((88) / 100) << 8) | (((88) / 100) << 16), \
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dx); \
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else \
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writel((95 / 100) | \
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((88 / 100) << 8) | ((88 / 100) << 16), dx)
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#define DMC_ENABLE_REGION(REGION) \
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writel(0xffffffff, REGION## _SEC_CFG); \
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writel(0x55555555, REGION## _SEC_WRITE_CTRL); \
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writel(0x55555555, REGION## _SEC_READ_CTRL)
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/* TODO: Timeout */
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#define WAIT_FOR(a) \
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while (!(readl(a) & 1)) \
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; \
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if (!(readl(a) & 1)) \
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panic("%s: init failed, err=%d", __func__, -ETIMEDOUT)
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/**
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* Register values
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**/
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/*
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* PLL
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*/
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#define DDR_CLK_CNTL_CLKGEN_SOFTRESET BIT(28)
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#define DDR_CLK_CNTL_PHY_CLK_ENABLE BIT(29)
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#define DDR_CLK_CNTL_DDRPLL_ENABLE BIT(31)
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/*
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* PCTL
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*/
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/* PCTL_SCTL: state control register (S905X datasheet p.451) */
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#define PCTL_SCTL_CFG_STATE BIT(0)
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#define PCTL_SCTL_GO_STATE BIT(1)
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/* PCTL_STAT */
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#define PCTL_STAT_ACCESS (BIT(1) | BIT(0))
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/* PCTL_POWCTL: power control */
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#define PCTL_POWCTL_POWERON BIT(0)
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/*
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* PUB
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*/
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/* PUB_PGSR0: PHY General Status Register 0 */
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#define PUB_PGSR0_IDONE BIT(0) /* Initialization Done */
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#define PUB_PGSR0_PLDONE BIT(1) /* PLL Lock Done */
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#define PUB_PGSR0_DCDONE BIT(2) /* DDL Calibration Done */
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#define PUB_PGSR0_ZCDONE BIT(3) /* Impedance Calibration Done */
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#define PUB_PGSR0_DIDONE BIT(4) /* DRAM Initialization Done */
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#define PUB_PGSR0_WLDONE BIT(5) /* Write Leveling Done */
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#define PUB_PGSR0_QSGDONE BIT(6) /* DQS Gate Training Done */
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#define PUB_PGSR0_WLADONE BIT(7) /* Write Leveling Adjust Done */
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#define PUB_PGSR0_RDDONE BIT(8) /* Read Bit Deskew Done */
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#define PUB_PGSR0_WDDONE BIT(9) /* Write Bit Deskew Done */
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#define PUB_PGSR0_REDONE BIT(10) /* Read Eye Training Done */
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#define PUB_PGSR0_WEDONE BIT(11) /* Write Eye Training Done */
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#define PUB_PGSR0_ZCERR BIT(20) /* Impedance Calib Error */
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#define PUB_PGSR0_WLERR BIT(21) /* Write Leveling Error */
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#define PUB_PGSR0_QSGERR BIT(22) /* DQS Gate Training Error */
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#define PUB_PGSR0_WLAERR BIT(23) /* Write Leveling Adj Error */
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#define PUB_PGSR0_RDERR BIT(24) /* Read Bit Deskew Error */
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#define PUB_PGSR0_WDERR BIT(25) /* Write Bit Deskew Error */
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#define PUB_PGSR0_REERR BIT(26) /* Read Eye Training Error */
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#define PUB_PGSR0_WEERR BIT(27) /* Write Eye Training Error */
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/* PUB_PIR: PHY init register */
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#define PUB_PIR_INIT BIT(0)
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#define PUB_PIR_ZCAL BIT(1)
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#define PUB_PIR_CA BIT(2)
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#define PUB_PIR_PLLINIT BIT(4)
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#define PUB_PIR_DCAL BIT(5)
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#define PUB_PIR_PHYRST BIT(6)
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#define PUB_PIR_DRAMRST BIT(7)
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#define PUB_PIR_DRAMINIT BIT(8)
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#define PUB_PIR_WL BIT(9)
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#define PUB_PIR_QSGATE BIT(10)
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#define PUB_PIR_WLADJ BIT(11)
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#define PUB_PIR_RDDSKW BIT(12)
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#define PUB_PIR_WRDSKW BIT(13)
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#define PUB_PIR_RDEYE BIT(14)
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#define PUB_PIR_WREYE BIT(15)
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#define PUB_PIR_ICPC BIT(16)
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#define PUB_PIR_PLLBYP BIT(17)
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#define PUB_PIR_CTLDINIT BIT(18)
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#define PUB_PIR_RDIMMINIT BIT(19)
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#define PUB_PIR_CLRSR BIT(27)
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#define PUB_PIR_LOCKBYP BIT(28)
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#define PUB_PIR_DCALBYP BIT(29)
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#define PUB_PIR_ZCALBYP BIT(30)
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#define PUB_PIR_INITBYP BIT(31)
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#define PUB_PIR_FINAL_STEP (PUB_PIR_INIT | PUB_PIR_ZCAL | \
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PUB_PIR_PLLINIT | PUB_PIR_DCAL | PUB_PIR_PHYRST | PUB_PIR_DRAMRST | \
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PUB_PIR_DRAMINIT | PUB_PIR_WL | PUB_PIR_QSGATE | PUB_PIR_WLADJ | \
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PUB_PIR_RDDSKW | PUB_PIR_WRDSKW | PUB_PIR_RDEYE | PUB_PIR_WREYE)
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/* Struct which holds timings (see dram-settings-gx.h) */
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struct meson_gx_dram_timings {
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u8 drv;
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u8 odt;
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u8 rtp;
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u8 wtr;
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u8 rp;
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u8 rcd;
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u8 ras;
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u8 rrd;
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u8 rc;
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u8 mrd;
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u8 mod;
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u8 faw;
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u8 wlmrd;
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u8 wlo;
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ushort rfc;
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u8 xp;
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ushort xs;
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ushort dllk;
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u8 cke;
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u8 rtodt;
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u8 rtw;
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u8 refi;
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u8 refi_mddr3;
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u8 cl;
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u8 wr;
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u8 cwl;
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u8 al;
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u8 dqs;
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u8 cksre;
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u8 cksrx;
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u8 zqcs;
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u8 xpdll;
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ushort exsr;
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ushort zqcl;
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ushort zqcsi;
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u8 rpab;
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u8 rppb;
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u8 tccdl;
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u8 tdqsck;
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u8 tdqsckmax;
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u8 tckesr;
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u8 tdpd;
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u8 taond_aofd;
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};
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#if defined(CONFIG_MESON_GXBB)
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# include <asm/arch/dram-gxbb.h>
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#elif defined(CONFIG_MESON_GXL)
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# include <asm/arch/dram-gxl.h>
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#endif
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/* Functions */
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int dram_init(void);
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void meson_dram_prepare_pctl(void);
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void meson_dram_phy_init(void);
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void meson_dram_phy_setup_ranks(void);
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void meson_dram_finalise_init(void);
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extern const struct meson_gx_dram_timings timings;
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#endif
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