Files
u-boot/drivers/sysreset/sysreset_qemu_virt_ctrl.c
Daniel Palmer 0bcd158db3 sysreset: qemu virt: Use __raw_writel()
The virt ctrl register seems to be native endian, currently this driver
uses writel(), which works by luck because its currently broken on m68k.

Use __raw_writel() instead to avoid breaking this driver when the
endianness of writel() is fixed.

Acked-by: Kuan-Wei Chiu <visitorckw@gmail.com>
Reviewed-by: Angelo Dureghello <angelo@kernel-space.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Daniel Palmer <daniel@thingy.jp>
2026-05-22 16:47:54 -06:00

58 lines
1.3 KiB
C

// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2025, Kuan-Wei Chiu <visitorckw@gmail.com>
*
* QEMU Virtual System Controller Driver
*/
#include <dm.h>
#include <qemu_virt_ctrl.h>
#include <sysreset.h>
#include <mapmem.h>
#include <asm/io.h>
#include <linux/err.h>
/* Register offsets */
#define VIRT_CTRL_REG_FEATURES 0x00
#define VIRT_CTRL_REG_CMD 0x04
/* Commands */
#define VIRT_CTRL_CMD_NOOP 0x00
#define VIRT_CTRL_CMD_RESET 0x01
#define VIRT_CTRL_CMD_HALT 0x02
#define VIRT_CTRL_CMD_PANIC 0x03
static int qemu_virt_ctrl_request(struct udevice *dev, enum sysreset_t type)
{
struct qemu_virt_ctrl_plat *plat = dev_get_plat(dev);
void __iomem *reg = map_sysmem(plat->reg + VIRT_CTRL_REG_CMD, 0x4);
u32 val;
switch (type) {
case SYSRESET_WARM:
case SYSRESET_COLD:
val = VIRT_CTRL_CMD_RESET;
break;
case SYSRESET_POWER_OFF:
val = VIRT_CTRL_CMD_HALT;
break;
default:
return -EPROTONOSUPPORT;
}
__raw_writel(val, reg);
return -EINPROGRESS;
}
static struct sysreset_ops qemu_virt_ctrl_ops = {
.request = qemu_virt_ctrl_request,
};
U_BOOT_DRIVER(sysreset_qemu_virt_ctrl) = {
.name = "sysreset_qemu_virt_ctrl",
.id = UCLASS_SYSRESET,
.ops = &qemu_virt_ctrl_ops,
.plat_auto = sizeof(struct qemu_virt_ctrl_plat),
};