Conor Dooley 4d056a2037 riscv: create a custom CPU implementation for PolarFire SoC ...

PolarFire SoC needs a custom implementation of top_of_ram(), so stop
using the generic CPU & create a custom CPU instead.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>

2025-12-08 12:10:39 +08:00

..

arch-andes

andes: Use UCCTLCOMMAND instead of MCCTLCOMMAND

2024-05-30 16:01:13 +08:00

arch-ast2700

ram: ast2700: Add DRAM controller initialization

2024-09-11 20:35:03 +08:00

arch-fu540

board: sifive: Rename spl_soc_init() to spl_dram_init()

2024-05-02 00:01:18 +08:00

arch-fu740

board: sifive: Rename spl_soc_init() to spl_dram_init()

2024-05-02 00:01:18 +08:00

arch-generic

dm: treewide: Rename ..._platdata variables to just ..._plat

2020-12-13 16:51:09 -07:00

arch-jh7110

spl: starfive: visionfive2: Disable USB overcurrent pin by default.

2025-03-17 01:55:19 +01:00

arch-mpfs

riscv: create a custom CPU implementation for PolarFire SoC

2025-12-08 12:10:39 +08:00

arch-th1520

riscv: cpu: th1520: Add a routine to bring up secondary cores

2025-07-03 16:14:13 +08:00

acpi_table.h

acpi: Add missing RISC-V acpi_table header

2023-08-02 11:02:33 +08:00

asm.h

…

atomic.h

riscv: add generic link for <asm/atomic.h>

2023-07-06 17:28:08 +08:00

barrier.h

…

bitops.h

riscv: define find_{first,next}_zero_bit in asm/bitops.h

2024-09-10 10:10:43 +08:00

byteorder.h

riscv: byteorder: add test for big-endian

2025-07-03 18:10:50 +08:00

cache.h

riscv: lib: modify the indent

2021-09-07 10:34:29 +08:00

config.h

Convert CONFIG_SYS_BOOT_RAMDISK_HIGH to Kconfig

2022-07-07 14:01:09 -04:00

cpufeature.h

riscv: Enhance extension probing

2025-01-16 15:34:18 +08:00

csr.h

andes: csr.h: Clean up CSR definition

2023-12-27 17:29:07 +08:00

dma-mapping.h

riscv: Remove common.h usage

2023-10-24 16:34:45 -04:00

encoding.h

arch/riscv: Remove unused macro in encoding.h

2025-09-19 19:23:17 +08:00

global_data.h

riscv: remove volatile from set_gd prototype

2025-06-13 16:57:15 -06:00

gpio.h

…

hwcap.h

riscv: Enhance extension probing

2025-01-16 15:34:18 +08:00

insn-def.h

riscv: insn-def.h: Fix header guard

2025-05-21 16:49:30 +08:00

io.h

riscv: io.h: Fix signatures of reads/writes functions

2023-11-28 16:19:06 -05:00

linkage.h

…

posix_types.h

…

processor.h

…

ptrace.h

…

sbi.h

cmd: sbi: Add FWFT, MPXY extensions

2024-10-28 16:11:33 +08:00

sections.h

…

setjmp.h

common: clean up setjmp.h

2025-03-10 07:41:16 +01:00

smp.h

riscv: Remove common.h usage

2023-10-24 16:34:45 -04:00

spl.h

common: spl: Add spl NVMe boot support

2023-06-19 17:47:41 -04:00

string.h

riscv: Add Zbb support for building U-Boot

2023-10-19 17:29:50 +08:00

syscon.h

riscv: Rename SiFive CLINT to RISC-V ALINT

2023-07-12 13:21:40 +08:00

system.h

event: Convert existing spy records to simple

2023-08-31 13:16:54 -04:00

types.h

riscv: Change phys_addr_t and phys_size_t to 64-bit

2021-02-03 03:38:41 -07:00

u-boot-riscv.h

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u-boot.h

Revert "riscv: Select appropriate image type"

2025-06-02 16:17:55 +08:00

unaligned.h

…