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Fix clock division factor initialization for RCC_PLLCFGR registers. PLLR bits (bit 31-28) in RCC_PLLCFGR must not be cleared, it's a forbidden value. So update RCC_PLLCFGR using clrsetbits_le32() to set only necessary bits fields. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>