mirror of
https://source.denx.de/u-boot/u-boot.git
synced 2026-06-02 09:46:37 +03:00
d05ef0f258
Today we typically enable CMD_SATA in order to have the SATA functionality itself enabled, despite there being a clean split between the two symbols. This in turn leads to potential configuration problems. Split things so that SATA continues to be separate and not CMD_SATA instead depends, functionally, on AHCI being enabled. To do all of this: - Have X86 select AHCI directly rather than "default y" it later. - Make CMD_SATA be a default y option, given the split of platforms that enabled SATA and did, or did not, enable CMD_SATA. - Change "imply CMD_SATA" to "imply SATA" - Correct TARGET_VEXPRESS64_JUNO because you cannot select SATA_SIL without PCI (and in turn, SATA is needed for SATA_SIL). - Update a number of defconfigs to have no functional change. Signed-off-by: Tom Rini <trini@konsulko.com>
111 lines
2.7 KiB
Plaintext
111 lines
2.7 KiB
Plaintext
CONFIG_ARM=y
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CONFIG_COUNTER_FREQUENCY=12500000
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CONFIG_TARGET_LS1021AIOT=y
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CONFIG_TEXT_BASE=0x82000000
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CONFIG_SYS_MALLOC_LEN=0x1002000
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CONFIG_SPL_LIBCOMMON_SUPPORT=y
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CONFIG_SPL_LIBGENERIC_SUPPORT=y
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CONFIG_NR_DRAM_BANKS=1
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CONFIG_ENV_SIZE=0x2000
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CONFIG_ENV_OFFSET=0x100000
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CONFIG_SYS_I2C_MXC_I2C1=y
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CONFIG_SYS_I2C_MXC_I2C2=y
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CONFIG_SYS_I2C_MXC_I2C3=y
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CONFIG_DM_GPIO=y
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CONFIG_DEFAULT_DEVICE_TREE="ls1021a-iot-duart"
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CONFIG_SYS_MONITOR_LEN=524288
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CONFIG_SPL_MMC=y
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CONFIG_SPL_SERIAL=y
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CONFIG_SPL_STACK=0x1001d000
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CONFIG_SPL_TEXT_BASE=0x10000000
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CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
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CONFIG_SPL_BSS_START_ADDR=0x80100000
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CONFIG_SPL_BSS_MAX_SIZE=0x80000
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CONFIG_SYS_LOAD_ADDR=0x82000000
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CONFIG_SPL=y
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CONFIG_PCI=y
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CONFIG_AHCI=y
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# CONFIG_DEEP_SLEEP is not set
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CONFIG_LAYERSCAPE_NS_ACCESS=y
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CONFIG_PCIE1=y
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CONFIG_PCIE2=y
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CONFIG_RAMBOOT_PBL=y
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CONFIG_SYS_FSL_PBL_PBI="board/nxp/ls1021aiot/ls102xa_pbi.cfg"
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CONFIG_SYS_FSL_PBL_RCW="board/nxp/ls1021aiot/ls102xa_rcw_sd.cfg"
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CONFIG_SD_BOOT=y
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CONFIG_SD_BOOT_QSPI=y
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CONFIG_OF_BOARD_SETUP=y
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CONFIG_OF_STDOUT_VIA_ALIAS=y
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CONFIG_SYS_CBSIZE=256
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CONFIG_SYS_PBSIZE=276
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CONFIG_BOARD_EARLY_INIT_F=y
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CONFIG_MISC_INIT_R=y
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CONFIG_ID_EEPROM=y
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CONFIG_SPL_MAX_SIZE=0x1a000
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CONFIG_SPL_PAD_TO=0x1c000
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CONFIG_SPL_FSL_PBL=y
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# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
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CONFIG_SPL_HAVE_INIT_STACK=y
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CONFIG_SPL_SYS_MALLOC=y
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CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
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CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x82080000
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CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
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CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8
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CONFIG_SPL_ENV_SUPPORT=y
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CONFIG_SPL_I2C=y
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CONFIG_SPL_MPC8XXX_INIT_DDR=y
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CONFIG_SPL_WATCHDOG=y
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CONFIG_CMD_BOOTZ=y
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CONFIG_CMD_GREPENV=y
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CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
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CONFIG_CMD_MEMINFO=y
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CONFIG_CMD_GPT=y
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CONFIG_CMD_I2C=y
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CONFIG_CMD_MMC=y
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# CONFIG_CMD_SATA is not set
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CONFIG_CMD_DHCP=y
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CONFIG_CMD_MII=y
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# CONFIG_CMD_MDIO is not set
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CONFIG_CMD_PING=y
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CONFIG_CMD_EXT2=y
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CONFIG_CMD_FAT=y
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# CONFIG_SPL_EFI_PARTITION is not set
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CONFIG_OF_CONTROL=y
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CONFIG_ENV_OVERWRITE=y
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CONFIG_ENV_IS_IN_MMC=y
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CONFIG_ENV_RELOC_GD_ENV_ADDR=y
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CONFIG_USE_ETHPRIME=y
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CONFIG_ETHPRIME="eTSEC2"
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CONFIG_SATA=y
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CONFIG_SATA_CEVA=y
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CONFIG_FSL_CAAM=y
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CONFIG_DM_I2C=y
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CONFIG_SPL_SYS_I2C_LEGACY=y
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CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
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CONFIG_SYS_I2C_EEPROM_ADDR=0x51
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CONFIG_FSL_IFC=y
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CONFIG_FSL_ESDHC=y
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CONFIG_MTD=y
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CONFIG_SPI_FLASH_ATMEL=y
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CONFIG_SPI_FLASH_SPANSION=y
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CONFIG_SPI_FLASH_STMICRO=y
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CONFIG_PHY_ATHEROS=y
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CONFIG_PHY_GIGE=y
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CONFIG_E1000=y
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CONFIG_MII=y
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CONFIG_TSEC_ENET=y
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CONFIG_NVME_PCI=y
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CONFIG_DM_PCI_COMPAT=y
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CONFIG_PCIE_LAYERSCAPE_RC=y
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CONFIG_U_QE=y
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CONFIG_SYS_QE_FW_ADDR=0xf40000
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CONFIG_DM_SERIAL=y
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CONFIG_SPL_SYS_NS16550_SERIAL=y
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CONFIG_SPI=y
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CONFIG_DM_SPI=y
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CONFIG_FSL_DSPI=y
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CONFIG_FSL_QSPI=y
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CONFIG_USB=y
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CONFIG_USB_XHCI_HCD=y
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CONFIG_USB_XHCI_DWC3=y
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