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Make sure RPC PHY timing registers are configured before performing bus access. These registers might have been left unconfigured or may have been configured by a prior stage bootloader and leaving them unconfigured or misconfigured would interfere with U-Boot operation. Set PHYOFFSET1 DDRTMG field to 3 which enables DDR timing adjustment when SPIDRE or DRDRE = 0 and set PHYOFFSET2 OCTTMG field to 4 which makes the interface operate in Serial flash or HyperFlash mode. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>