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d62801d094
Rockchip SoCs typically reset with all (or most) clocks ungated. Because of this, U-Boot clock drivers for Rockchip typically do not implement the optional clk-uclass enable/disable ops. Normal driver model behavior is to return -ENOSYS when an uclass ops is not implemented. Ignore -ENOSYS to allow the designware watchdog driver to be probed on platforms that do not implement the clk-uclass enable/disable ops, e.g. Rockchip RK3308. Signed-off-by: Jonas Karlman <jonas@kwiboo.se>