Parthiban Nallathambi
d8d33b6d4d
imx: Add variscite DART-6UL Evaluation Kit
Port for the DART-6UL Evaluation Kit SBC. Based on the variscite
DART-6UL iMX6ULL SoM.
CPU: Freescale i.MX6ULL rev1.1 900 MHz (running at 396 MHz)
CPU: Commercial temperature grade (0C to 95C) at 43C
Reset cause: POR
Model: Variscite DART-6UL Evaluation Kit
Board: Variscite DART-6UL Evaluation Kit
DRAM: 512 MiB
MMC: FSL_SDHC: 0, FSL_SDHC: 1
In: serial@02020000
Out: serial@02020000
Err: serial@02020000
Net: FEC0
Working:
- Eth0
- i2c
- MMC/SD
- eMMC
- USB host
- UART 1
Note: LCDIF porting needs DM_VIDEO
https://lists.denx.de/pipermail/u-boot/2019-April/365506.html
Signed-off-by: Parthiban Nallathambi <parthitce@gmail.com>
2019-04-25 19:16:24 +02:00
..
2019-04-23 17:57:28 -04:00
2019-04-25 19:16:24 +02:00
2019-04-25 19:16:24 +02:00
2019-04-22 18:13:24 -04:00
2019-04-18 09:43:22 +03:00
2019-01-18 09:16:15 -05:00
2018-11-05 10:41:59 -06:00
2019-03-25 17:35:52 -04:00
2019-04-25 19:16:24 +02:00
2019-04-12 08:05:52 -04:00
2019-04-12 08:05:46 -04:00
2019-04-12 07:04:18 +02:00
2019-04-23 17:57:26 -04:00
2019-01-31 09:35:01 +01:00
2019-04-12 07:04:18 +02:00
2019-04-17 09:20:26 -04:00
2018-10-10 13:35:09 -04:00
2019-04-09 18:19:10 +02:00
2019-03-29 09:21:13 +01:00
2019-02-09 12:50:21 -07:00
2019-01-25 12:12:56 -05:00
2019-04-17 22:20:17 +02:00
2018-10-06 14:09:41 -04:00
2019-04-12 16:09:13 +02:00
2019-04-17 14:34:45 +05:30
2019-01-24 10:03:44 +01:00
2018-12-29 11:38:33 +09:00
2019-02-14 14:31:10 +01:00
2019-02-14 14:31:10 +01:00
2019-04-16 11:52:02 +02:00
2019-04-25 19:16:24 +02:00
2019-01-28 20:35:47 +01:00