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Hrushikesh Salunke <h-salunke@ti.com> says: This series enables PCIe Endpoint mode on TI's J784S4 SoC. The J784S4 SoC features two Cadence PCIe controller instances (PCIe0 and PCIe1) that can operate in endpoint mode. This series adds support for configuring these controllers with up to 4 lanes. Key changes include: - Adding a stabilization delay after power domain reset to prevent timing-related initialization issues - SERDES mux configuration support for proper lane routing, which is essential for SoCs where SERDES lanes are shared between multiple controllers (PCIe, USB, etc.) with different configurations across boot phases - J784S4 SoC endpoint configuration with 4-lane support - Disabling unconfigured endpoint functions to prevent enumeration issues on the Root Complex side This series has been tested on J784S4 EVM with PCIe endpoint boot configuration. Following are the corresponding test logs. https://gist.github.com/hrushikesh221/331d65f45f43fd138f57e6adb61c4332 Link: https://lore.kernel.org/r/20251023114604.3655625-1-h-salunke@ti.com