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Some Renesas SoCs, such as the RZ/G2L, require the USBHS core to be explicitly deasserted from reset before register access is possible. Update the OTG probe to handle a bulk reset controller. To maintain hardware stability, the reset is deasserted after clocks are enabled in probe(), and asserted before clocks are disabled in remove(). Update the error paths in probe to ensures clocks are disabled if the reset initialization fails. Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Signed-off-by: Michele Bisogno <micbis.openwrt@gmail.com>