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11d5655919
On DTR capable flashes like Micron Xcella the writes cannot start or end at an odd address in DTR mode. Extra 0xff bytes need to be prepended or appended respectively to make sure both the start and end addresses are even. Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Signed-off-by: Apurva Nandan <a-nandan@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Jonathan Humphreys <j-humphreys@ti.com> Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>