Yao Zi 5fe9ced355 riscv: cpu: Add TH1520 CPU support ...

Introduce the SoC-specific code and corresponding Kconfig entries for
TH1520 SoC. Following features are implemented for TH1520,

- Cache enable/disable through customized CSR
- Invalidation of customized PMP entries
- DRAM driver probing for SPL

Signed-off-by: Yao Zi <ziyao@disroot.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>

2025-05-21 16:49:52 +08:00

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arch-andes

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arch-ast2700

ram: ast2700: Add DRAM controller initialization

2024-09-11 20:35:03 +08:00

arch-fu540

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arch-fu740

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arch-generic

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arch-jh7110

spl: starfive: visionfive2: Disable USB overcurrent pin by default.

2025-03-17 01:55:19 +01:00

arch-th1520

riscv: cpu: Add TH1520 CPU support

2025-05-21 16:49:52 +08:00

acpi_table.h

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asm.h

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atomic.h

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barrier.h

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bitops.h

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byteorder.h

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cache.h

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config.h

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cpufeature.h

riscv: Enhance extension probing

2025-01-16 15:34:18 +08:00

csr.h

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dma-mapping.h

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encoding.h

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global_data.h

riscv: Access gd with inline assembly when building with LTO or Clang

2025-05-21 16:46:16 +08:00

gpio.h

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hwcap.h

riscv: Enhance extension probing

2025-01-16 15:34:18 +08:00

insn-def.h

riscv: insn-def.h: Fix header guard

2025-05-21 16:49:30 +08:00

io.h

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linkage.h

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posix_types.h

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processor.h

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ptrace.h

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sbi.h

cmd: sbi: Add FWFT, MPXY extensions

2024-10-28 16:11:33 +08:00

sections.h

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setjmp.h

common: clean up setjmp.h

2025-03-10 07:41:16 +01:00

smp.h

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spl.h

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string.h

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syscon.h

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system.h

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types.h

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u-boot-riscv.h

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u-boot.h

riscv: Select appropriate image type

2025-05-21 16:45:55 +08:00

unaligned.h

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