Bin Meng ea53f1c742 riscv: Add CSR numbers ...

The standard RISC-V ISA sets aside a 12-bit encoding space for up
to 4096 CSRs. This adds all known CSR numbers as defined in the
RISC-V Privileged Architecture Version 1.10.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup@brainfault.org>

2018-12-18 09:56:27 +08:00

..

arc

ARC: Improve identification of ARC cores

2018-12-03 14:26:18 +03:00

arm

Merge tag 'for-master-20181216' of git://git.denx.de/u-boot-rockchip

2018-12-16 20:49:46 -05:00

m68k

m68k: ColdFire mcf5441x, add eSDHC support

2018-09-16 00:01:13 +02:00

microblaze

arch: types.h: factor out fixed width typedefs to int-ll64.h

2018-09-10 20:48:16 -04:00

mips

bmips: bcm6838: fix device tree warning

2018-12-10 18:47:13 +01:00

nds32

Drop CONFIG_INIT_CRITICAL

2018-11-26 13:57:31 +08:00

nios2

.gitignore: move *.dtb and *.dtb.S patterns to the top-level .gitignore

2018-06-18 14:43:12 -04:00

powerpc

Merge branch 'master' of git://git.denx.de/u-boot-spi

2018-12-05 15:06:24 -05:00

riscv

riscv: Add CSR numbers

2018-12-18 09:56:27 +08:00

sandbox

dm: sandbox: Allow selection of sample rate and channels

2018-12-13 16:37:09 -07:00

sh

Kbuild: add LDFLAGS_STANDALONE

2018-11-18 16:02:23 +01:00

x86

efi: payload: only init usb if necessary

2018-12-10 10:14:42 +08:00

xtensa

xtensa: use asm-generic/atomic.h

2018-09-25 21:49:18 -04:00

.gitignore

…

Kconfig

dm: sound: Create an option to use driver model for sound

2018-12-13 16:32:49 -07:00