Files
u-boot/arch/arm/cpu/armv7m/cpu.c
Anshul Dalal 16ffcff028 spl: split spl_board_fixups to arch/board specific
The current spl_board_fixups API allows for modification of spl_image
before the SPL jumps to it. This can be used to modify the DT for the
next boot stage, however the current API only allows either the machine
arch or the board to use it.

This limits the utility of the API as there might be certain fixups that
should be applied to all boards sharing the same machine architecture
with others being board specific.

For TI's K3 specifically, this prevents us from performing architecture
level fixups since a lot of TI boards are already making use of the
spl_board_fixups API.

Therefore this patch splits the API into two to allow both board and the
architecture specific fixups. The order is kept as arch then board to
give board specific fixups the precedence.

Reviewed-by: Dhruva Gole <d-gole@ti.com>
Signed-off-by: Anshul Dalal <anshuld@ti.com>
Tested-by: Wadim Egorov <w.egorov@phytec.de>
2025-10-22 12:05:52 -06:00

64 lines
1.4 KiB
C

// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2010,2011
* Vladimir Khusainov, Emcraft Systems, vlad@emcraft.com
*
* (C) Copyright 2015
* Kamil Lulko, <kamil.lulko@gmail.com>
*/
#include <cpu_func.h>
#include <irq_func.h>
#include <asm/io.h>
#include <asm/armv7m.h>
#include <spl.h>
/*
* This is called right before passing control to
* the Linux kernel point.
*/
int cleanup_before_linux(void)
{
/*
* this function is called just before we call linux
* it prepares the processor for linux
*
* disable interrupt and turn off caches etc ...
*/
disable_interrupts();
/*
* turn off D-cache
* dcache_disable() in turn flushes the d-cache
* MPU is still enabled & can't be disabled as the u-boot
* code might be running in sdram which by default is not
* executable area.
*/
dcache_disable();
/* invalidate to make sure no cache line gets dirty between
* dcache flushing and disabling dcache */
invalidate_dcache_all();
icache_disable();
invalidate_icache_all();
return 0;
}
/*
* Perform the low-level reset.
*/
void reset_cpu(void)
{
/*
* Perform reset but keep priority group unchanged.
*/
writel((V7M_AIRCR_VECTKEY << V7M_AIRCR_VECTKEY_SHIFT)
| (V7M_SCB->aircr & V7M_AIRCR_PRIGROUP_MSK)
| V7M_AIRCR_SYSRESET, &V7M_SCB->aircr);
}
void spl_perform_arch_fixups(struct spl_image_info *spl_image)
{
spl_image->entry_point |= 0x1;
}