Files
u-boot/arch
Kever Yang faa75ad9e6 rockchip: rk3036: fix pll config for correct frequency
There is a fixed div-2 between PLL and clk_ddr/clk_ddrphy,
so we need to double to pll output and then ddr can work
in correct frequency.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-30 22:55:27 +01:00
..
2017-10-02 21:52:20 -04:00
2017-11-30 10:04:21 +08:00
2017-10-02 21:52:21 -04:00
2017-10-02 21:52:22 -04:00