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Reformat spacing/comments in src/jtagmkII_private.h
This commit is contained in:
Stefan Rueger
@@ -17,17 +17,17 @@
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/*
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* JTAG ICE mkII definitions
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* Taken from Appnote AVR067
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*/
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#if !defined(JTAGMKII_PRIVATE_EXPORTED)
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/*
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* Communication with the JTAG ICE works in frames. The protocol
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* somewhat resembles the STK500v2 protocol, yet it is sufficiently
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* different to prevent a direct code reuse. :-(
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* Communication with the JTAG ICE works in frames. The protocol somewhat
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* resembles the STK500v2 protocol, yet it is sufficiently different to prevent
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* a direct code reuse. :-(
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*
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* Frame format:
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*
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@@ -60,18 +60,16 @@
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#define TOKEN 0x0e
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/*
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* Max message size we are willing to accept. Prevents us from trying
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* to allocate too much VM in case we received a nonsensical packet
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* length. We have to allocate the buffer as soon as we've got the
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* length information (and thus have to trust that information by that
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* time at first), as the final CRC check can only be done once the
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* entire packet came it.
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* Max message size we are willing to accept. Prevents us from trying to
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* allocate too much VM in case we received a nonsensical packet length. We
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* have to allocate the buffer as soon as we've got the length information (and
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* thus have to trust that information by that time at first), as the final CRC
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* check can only be done once the entire packet came it.
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*/
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#define MAX_MESSAGE 100000
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#endif // JTAGMKII_PRIVATE_EXPORTED
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#endif /* JTAGMKII_PRIVATE_EXPORTED */
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/* ICE command codes */
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// ICE command codes
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#define CMND_SIGN_OFF 0x00
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#define CMND_GET_SIGN_ON 0x01
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#define CMND_SET_PARAMETER 0x02
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@@ -108,10 +106,9 @@
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#define CMND_WRITE_MEMORY32 0x2D
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#define CMND_ISP_PACKET 0x2F
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#define CMND_XMEGA_ERASE 0x34
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#define CMND_SET_XMEGA_PARAMS 0x36 // undocumented in AVR067
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#define CMND_SET_XMEGA_PARAMS 0x36 // Undocumented in AVR067
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/* ICE responses */
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// ICE responses
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#define RSP_OK 0x80
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#define RSP_PARAMETER 0x81
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#define RSP_MEMORY 0x82
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@@ -135,7 +132,7 @@
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#define RSP_DEBUGWIRE_SYNC_FAILED 0xAC
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#define RSP_ILLEGAL_POWER_STATE 0xAD
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/* ICE events */
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// ICE events
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#define EVT_BREAK 0xE0
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#define EVT_RUN 0xE1
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#define EVT_ERROR_PHY_FORCE_BREAK_TIMEOUT 0xE2
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@@ -164,69 +161,72 @@
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#define EVT_ERROR_PHY_OPT_RECEIVED_BREAK 0xFA
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#define EVT_RESULT_PHY_NO_ACTIVITY 0xFB
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/* memories for CMND_{READ,WRITE}_MEMORY */
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#define MTYPE_IO_SHADOW 0x30 /* cached IO registers? */
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#define MTYPE_SRAM 0x20 /* target's SRAM or [ext.] IO registers */
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#define MTYPE_EEPROM 0x22 /* EEPROM, what way? */
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#define MTYPE_EVENT 0x60 /* ICE event memory */
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#define MTYPE_SPM 0xA0 /* flash through LPM/SPM */
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#define MTYPE_FLASH_PAGE 0xB0 /* flash in programming mode */
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#define MTYPE_EEPROM_PAGE 0xB1 /* EEPROM in programming mode */
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#define MTYPE_FUSE_BITS 0xB2 /* fuse bits in programming mode */
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#define MTYPE_LOCK_BITS 0xB3 /* lock bits in programming mode */
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#define MTYPE_SIGN_JTAG 0xB4 /* signature in programming mode */
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#define MTYPE_OSCCAL_BYTE 0xB5 /* osccal cells in programming mode */
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#define MTYPE_CAN 0xB6 /* CAN mailbox */
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#define MTYPE_FLASH 0xc0 /* xmega (app.) flash - undocumented in AVR067 */
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#define MTYPE_BOOT_FLASH 0xc1 /* xmega boot flash - undocumented in AVR067 */
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#define MTYPE_EEPROM_XMEGA 0xc4 /* xmega EEPROM in debug mode - undocumented in AVR067 */
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#define MTYPE_USERSIG 0xc5 /* xmega user signature - undocumented in AVR067 */
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#define MTYPE_PRODSIG 0xc6 /* xmega production signature - undocumented in AVR067 */
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// Memories for CMND_{READ,WRITE}_MEMORY
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#define MTYPE_IO_SHADOW 0x30 // Cached IO registers?
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#define MTYPE_SRAM 0x20 // Target's SRAM or [ext.] IO registers
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#define MTYPE_EEPROM 0x22 // EEPROM, what way?
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#define MTYPE_EVENT 0x60 // ICE event memory
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#define MTYPE_SPM 0xA0 // Flash through LPM/SPM
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#define MTYPE_FLASH_PAGE 0xB0 // Flash in programming mode
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#define MTYPE_EEPROM_PAGE 0xB1 // EEPROM in programming mode
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#define MTYPE_FUSE_BITS 0xB2 // Fuse bits in programming mode
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#define MTYPE_LOCK_BITS 0xB3 // Lock bits in programming mode
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#define MTYPE_SIGN_JTAG 0xB4 // Signature in programming mode
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#define MTYPE_OSCCAL_BYTE 0xB5 // Osccal cells in programming mode
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#define MTYPE_CAN 0xB6 // CAN mailbox
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#define MTYPE_FLASH 0xc0 // Xmega (app.) flash - undocumented in AVR067
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#define MTYPE_BOOT_FLASH 0xc1 // Xmega boot flash - undocumented in AVR067
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#define MTYPE_EEPROM_XMEGA 0xc4 // Xmega EEPROM in debug mode - undocumented in AVR067
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#define MTYPE_USERSIG 0xc5 // Xmega user signature - undocumented in AVR067
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#define MTYPE_PRODSIG 0xc6 // Xmega production signature - undocumented in AVR067
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/* (some) ICE parameters, for CMND_{GET,SET}_PARAMETER */
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// (Some) ICE parameters, for CMND_{GET,SET}_PARAMETER
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#define PAR_HW_VERSION 0x01
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#define PAR_FW_VERSION 0x02
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#define PAR_EMULATOR_MODE 0x03
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# define EMULATOR_MODE_DEBUGWIRE 0x00
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# define EMULATOR_MODE_JTAG 0x01
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# define EMULATOR_MODE_HV 0x02 /* HVSP or PP mode of AVR Dragon */
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# define EMULATOR_MODE_SPI 0x03
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# define EMULATOR_MODE_JTAG_AVR32 0x04
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# define EMULATOR_MODE_JTAG_XMEGA 0x05
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# define EMULATOR_MODE_PDI 0x06
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#define EMULATOR_MODE_DEBUGWIRE 0x00
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#define EMULATOR_MODE_JTAG 0x01
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#define EMULATOR_MODE_HV 0x02 // HVSP or PP mode of AVR Dragon
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#define EMULATOR_MODE_SPI 0x03
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#define EMULATOR_MODE_JTAG_AVR32 0x04
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#define EMULATOR_MODE_JTAG_XMEGA 0x05
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#define EMULATOR_MODE_PDI 0x06
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#define PAR_IREG 0x04
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#define PAR_BAUD_RATE 0x05
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# define PAR_BAUD_2400 0x01
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# define PAR_BAUD_4800 0x02
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# define PAR_BAUD_9600 0x03
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# define PAR_BAUD_19200 0x04 /* default */
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# define PAR_BAUD_38400 0x05
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# define PAR_BAUD_57600 0x06
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# define PAR_BAUD_115200 0x07
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# define PAR_BAUD_14400 0x08
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/* Extension to jtagmkII protocol: extra baud rates, standard series. */
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# define PAR_BAUD_153600 0x09
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# define PAR_BAUD_230400 0x0A
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# define PAR_BAUD_460800 0x0B
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# define PAR_BAUD_921600 0x0C
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/* Extension to jtagmkII protocol: extra baud rates, binary series. */
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# define PAR_BAUD_128000 0x0D
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# define PAR_BAUD_256000 0x0E
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# define PAR_BAUD_512000 0x0F
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# define PAR_BAUD_1024000 0x10
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/* Extension to jtagmkII protocol: extra baud rates, decimal series. */
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# define PAR_BAUD_150000 0x11
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# define PAR_BAUD_200000 0x12
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# define PAR_BAUD_250000 0x13
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# define PAR_BAUD_300000 0x14
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# define PAR_BAUD_400000 0x15
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# define PAR_BAUD_500000 0x16
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# define PAR_BAUD_600000 0x17
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# define PAR_BAUD_666666 0x18
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# define PAR_BAUD_1000000 0x19
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# define PAR_BAUD_1500000 0x1A
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# define PAR_BAUD_2000000 0x1B
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# define PAR_BAUD_3000000 0x1C
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#define PAR_BAUD_2400 0x01
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#define PAR_BAUD_4800 0x02
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#define PAR_BAUD_9600 0x03
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#define PAR_BAUD_19200 0x04 // Default
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#define PAR_BAUD_38400 0x05
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#define PAR_BAUD_57600 0x06
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#define PAR_BAUD_115200 0x07
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#define PAR_BAUD_14400 0x08
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// Extension to jtagmkII protocol: extra baud rates, standard series
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#define PAR_BAUD_153600 0x09
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#define PAR_BAUD_230400 0x0A
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#define PAR_BAUD_460800 0x0B
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#define PAR_BAUD_921600 0x0C
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// Extension to jtagmkII protocol: extra baud rates, binary series
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#define PAR_BAUD_128000 0x0D
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#define PAR_BAUD_256000 0x0E
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#define PAR_BAUD_512000 0x0F
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#define PAR_BAUD_1024000 0x10
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// Extension to jtagmkII protocol: extra baud rates, decimal series
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#define PAR_BAUD_150000 0x11
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#define PAR_BAUD_200000 0x12
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#define PAR_BAUD_250000 0x13
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#define PAR_BAUD_300000 0x14
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#define PAR_BAUD_400000 0x15
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#define PAR_BAUD_500000 0x16
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#define PAR_BAUD_600000 0x17
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#define PAR_BAUD_666666 0x18
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#define PAR_BAUD_1000000 0x19
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#define PAR_BAUD_1500000 0x1A
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#define PAR_BAUD_2000000 0x1B
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#define PAR_BAUD_3000000 0x1C
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#define PAR_OCD_VTARGET 0x06
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#define PAR_OCD_JTAG_CLK 0x07
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#define PAR_OCD_BREAK_CAUSE 0x08
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@@ -248,9 +248,9 @@
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#define PAR_PSB1 0x18
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#define PAR_PROTOCOL_DEBUG_EVENT 0x19
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#define PAR_MCU_STATE 0x1A
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# define STOPPED 0x00
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# define RUNNING 0x01
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# define PROGRAMMING 0x02
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#define STOPPED 0x00
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#define RUNNING 0x01
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#define PROGRAMMING 0x02
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#define PAR_DAISY_CHAIN_INFO 0x1B
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#define PAR_BOOT_ADDRESS 0x1C
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#define PAR_TARGET_SIGNATURE 0x1D
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@@ -264,19 +264,19 @@
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#define PAR_INTERCOMMUNICATION_RX_FAILURES 0x43
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#define PAR_CRC_ERRORS 0x44
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#define PAR_POWER_SOURCE 0x45
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# define POWER_EXTERNAL 0x00
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# define POWER_USB 0x01
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#define POWER_EXTERNAL 0x00
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#define POWER_USB 0x01
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#define PAR_CAN_FLAG 0x22
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# define DONT_READ_CAN_MAILBOX 0x00
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# define READ_CAN_MAILBOX 0x01
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#define DONT_READ_CAN_MAILBOX 0x00
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#define READ_CAN_MAILBOX 0x01
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#define PAR_ENABLE_IDR_IN_RUN_MODE 0x23
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# define ACCESS_OSCCAL 0x00
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# define ACCESS_IDR 0x01
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#define ACCESS_OSCCAL 0x00
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#define ACCESS_IDR 0x01
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#define PAR_ALLOW_PAGEPROGRAMMING_IN_SCANCHAIN 0x24
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# define PAGEPROG_NOT_ALLOWED 0x00
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# define PAGEPROG_ALLOWED 0x01
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#define PAGEPROG_NOT_ALLOWED 0x00
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#define PAGEPROG_ALLOWED 0x01
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/* Xmega erase memories for CMND_XMEGA_ERASE */
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// Xmega erase memories for CMND_XMEGA_ERASE
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#define XMEGA_ERASE_CHIP 0x00
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#define XMEGA_ERASE_APP 0x01
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#define XMEGA_ERASE_BOOT 0x02
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@@ -286,127 +286,116 @@
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#define XMEGA_ERASE_EEPROM_PAGE 0x06
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#define XMEGA_ERASE_USERSIG 0x07
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/* AVR32 related definitions */
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#define AVR32_FLASHC_FCR 0xFFFE1400
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#define AVR32_FLASHC_FCMD 0xFFFE1404
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#define AVR32_FLASHC_FCMD_KEY 0xA5000000
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#define AVR32_FLASHC_FCMD_WRITE_PAGE 1
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#define AVR32_FLASHC_FCMD_ERASE_PAGE 2
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#define AVR32_FLASHC_FCMD_CLEAR_PAGE_BUFFER 3
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#define AVR32_FLASHC_FCMD_LOCK 4
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#define AVR32_FLASHC_FCMD_UNLOCK 5
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#define AVR32_FLASHC_FSR 0xFFFE1408
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#define AVR32_FLASHC_FSR_RDY 0x00000001
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#define AVR32_FLASHC_FSR_ERR 0x00000008
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#define AVR32_FLASHC_FGPFRHI 0xFFFE140C
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#define AVR32_FLASHC_FGPFRLO 0xFFFE1410
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// AVR32 related definitions
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#define AVR32_FLASHC_FCR 0xFFFE1400
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#define AVR32_FLASHC_FCMD 0xFFFE1404
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#define AVR32_FLASHC_FCMD_KEY 0xA5000000
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#define AVR32_FLASHC_FCMD_WRITE_PAGE 1
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#define AVR32_FLASHC_FCMD_ERASE_PAGE 2
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#define AVR32_FLASHC_FCMD_CLEAR_PAGE_BUFFER 3
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#define AVR32_FLASHC_FCMD_LOCK 4
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#define AVR32_FLASHC_FCMD_UNLOCK 5
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#define AVR32_FLASHC_FSR 0xFFFE1408
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#define AVR32_FLASHC_FSR_RDY 0x00000001
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#define AVR32_FLASHC_FSR_ERR 0x00000008
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#define AVR32_FLASHC_FGPFRHI 0xFFFE140C
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#define AVR32_FLASHC_FGPFRLO 0xFFFE1410
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#define AVR32_DC 0x00000008
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#define AVR32_DS 0x00000010
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#define AVR32_DINST 0x00000104
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#define AVR32_DCCPU 0x00000110
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#define AVR32_DCEMU 0x00000114
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#define AVR32_DCSR 0x00000118
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#define AVR32_DC 0x00000008
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#define AVR32_DS 0x00000010
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#define AVR32_DINST 0x00000104
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#define AVR32_DCCPU 0x00000110
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#define AVR32_DCEMU 0x00000114
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#define AVR32_DCSR 0x00000118
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#define AVR32_DC_ABORT 0x80000000
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#define AVR32_DC_RESET 0x40000000
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#define AVR32_DC_DBE 0x00002000
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#define AVR32_DC_DBR 0x00001000
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#define AVR32_DC_ABORT 0x80000000
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#define AVR32_DC_RESET 0x40000000
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#define AVR32_DC_DBE 0x00002000
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#define AVR32_DC_DBR 0x00001000
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#define AVR32_RESET_READ 0x0001
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#define AVR32_RESET_WRITE 0x0002
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#define AVR32_RESET_CHIP_ERASE 0x0004
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#define AVR32_SET4RUNNING 0x0008
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//#define AVR32_RESET_COMMON (AVR32_RESET_READ | AVR32_RESET_WRITE | AVR32_RESET_CHIP_ERASE )
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// #define AVR32_RESET_COMMON (AVR32_RESET_READ | AVR32_RESET_WRITE | AVR32_RESET_CHIP_ERASE)
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#define DATA_OFFSET 0x1000000
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typedef enum
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{
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typedef enum {
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RTS_MODE_DEFAULT,
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RTS_MODE_LOW,
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RTS_MODE_HIGH
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} jtagmkii_rts_mode;
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#if !defined(JTAGMKII_PRIVATE_EXPORTED)
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/*
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* In appnote AVR067, struct device_descriptor is written with
|
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* int/long field types. We cannot use them directly, as they were
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* neither properly aligned for portability, nor did they care for
|
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* endianness issues. We thus use arrays of unsigned chars, plus
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* conversion macros.
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* In appnote AVR067, struct device_descriptor is written with int/long field
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* types. We cannot use them directly, as they were neither properly aligned
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* for portability, nor did they care for endianness issues. We thus use
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* arrays of unsigned chars, plus conversion macros.
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*/
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struct device_descriptor
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{
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unsigned char ucReadIO[8]; /*LSB = IOloc 0, MSB = IOloc63 */
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unsigned char ucReadIOShadow[8]; /*LSB = IOloc 0, MSB = IOloc63 */
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unsigned char ucWriteIO[8]; /*LSB = IOloc 0, MSB = IOloc63 */
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unsigned char ucWriteIOShadow[8]; /*LSB = IOloc 0, MSB = IOloc63 */
|
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unsigned char ucReadExtIO[52]; /*LSB = IOloc 96, MSB = IOloc511 */
|
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unsigned char ucReadIOExtShadow[52]; /*LSB = IOloc 96, MSB = IOloc511 */
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unsigned char ucWriteExtIO[52]; /*LSB = IOloc 96, MSB = IOloc511 */
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unsigned char ucWriteIOExtShadow[52];/*LSB = IOloc 96, MSB = IOloc511 */
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unsigned char ucIDRAddress; /*IDR address */
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unsigned char ucSPMCRAddress; /*SPMCR Register address and dW BasePC */
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||||
unsigned char ucRAMPZAddress; /*RAMPZ Register address in SRAM I/O */
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||||
/*space */
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||||
unsigned char uiFlashPageSize[2]; /*Device Flash Page Size, Size = */
|
||||
/*2 exp ucFlashPageSize */
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||||
unsigned char ucEepromPageSize; /*Device Eeprom Page Size in bytes */
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||||
unsigned char ulBootAddress[4]; /*Device Boot Loader Start Address */
|
||||
unsigned char uiUpperExtIOLoc[2]; /*Topmost (last) extended I/O */
|
||||
/*location, 0 if no external I/O */
|
||||
unsigned char ulFlashSize[4]; /*Device Flash Size */
|
||||
unsigned char ucEepromInst[20]; /*Instructions for W/R EEPROM */
|
||||
unsigned char ucFlashInst[3]; /*Instructions for W/R FLASH */
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unsigned char ucSPHaddr; /* stack pointer high */
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||||
unsigned char ucSPLaddr; /* stack pointer low */
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||||
/* new as of 16-02-2004 */
|
||||
unsigned char uiFlashpages[2]; /* number of pages in flash */
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||||
unsigned char ucDWDRAddress; /* DWDR register address */
|
||||
unsigned char ucDWBasePC; /* base/mask value of the PC */
|
||||
/* new as of 30-04-2004 */
|
||||
unsigned char ucAllowFullPageBitstream; /* FALSE on ALL new */
|
||||
/*parts */
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||||
unsigned char uiStartSmallestBootLoaderSection[2]; /* */
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||||
/* new as of 18-10-2004 */
|
||||
unsigned char EnablePageProgramming; /* For JTAG parts only, */
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||||
/* default TRUE */
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||||
unsigned char ucCacheType; /* CacheType_Normal 0x00, */
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||||
/* CacheType_CAN 0x01, */
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||||
/* CacheType_HEIMDALL 0x02 */
|
||||
/* new as of 27-10-2004 */
|
||||
unsigned char uiSramStartAddr[2]; /* Start of SRAM */
|
||||
unsigned char ucResetType; /* Selects reset type. ResetNormal = 0x00 */
|
||||
/* ResetAT76CXXX = 0x01 */
|
||||
unsigned char ucPCMaskExtended; /* For parts with extended PC */
|
||||
unsigned char ucPCMaskHigh; /* PC high mask */
|
||||
unsigned char ucEindAddress; /* Selects reset type. [EIND address...] */
|
||||
/* new as of early 2005, firmware 4.x */
|
||||
unsigned char EECRAddress[2]; /* EECR memory-mapped IO address */
|
||||
struct device_descriptor {
|
||||
unsigned char ucReadIO[8]; // LSB = IOloc 0, MSB = IOloc63
|
||||
unsigned char ucReadIOShadow[8]; // LSB = IOloc 0, MSB = IOloc63
|
||||
unsigned char ucWriteIO[8]; // LSB = IOloc 0, MSB = IOloc63
|
||||
unsigned char ucWriteIOShadow[8]; // LSB = IOloc 0, MSB = IOloc63
|
||||
unsigned char ucReadExtIO[52]; // LSB = IOloc 96, MSB = IOloc511
|
||||
unsigned char ucReadIOExtShadow[52]; // LSB = IOloc 96, MSB = IOloc511
|
||||
unsigned char ucWriteExtIO[52]; // LSB = IOloc 96, MSB = IOloc511
|
||||
unsigned char ucWriteIOExtShadow[52]; // LSB = IOloc 96, MSB = IOloc511
|
||||
unsigned char ucIDRAddress; // IDR address
|
||||
unsigned char ucSPMCRAddress; // SPMCR Register address and dW BasePC
|
||||
unsigned char ucRAMPZAddress; // Rampz Register address in SRAM I/O Space
|
||||
unsigned char uiFlashPageSize[2]; // Device Flash Page Size, Size = 2 exp ucFlashPageSize
|
||||
unsigned char ucEepromPageSize; // Device Eeprom Page Size in bytes
|
||||
unsigned char ulBootAddress[4]; // Device Boot Loader Start Address
|
||||
unsigned char uiUpperExtIOLoc[2]; // Topmost (last) extended I/O location, 0 if no external I/O
|
||||
unsigned char ulFlashSize[4]; // Device Flash Size
|
||||
unsigned char ucEepromInst[20]; // Instructions for W/R EEPROM
|
||||
unsigned char ucFlashInst[3]; // Instructions for W/R FLASH
|
||||
unsigned char ucSPHaddr; // Stack pointer high
|
||||
unsigned char ucSPLaddr; // Stack pointer low; new as of 16-02-2004
|
||||
unsigned char uiFlashpages[2]; // Number of pages in flash
|
||||
unsigned char ucDWDRAddress; // DWDR register address
|
||||
unsigned char ucDWBasePC; // Base/mask value of the PC; new as of 30-04-2004
|
||||
unsigned char ucAllowFullPageBitstream; // False on ALL new parts
|
||||
unsigned char uiStartSmallestBootLoaderSection[2];
|
||||
// New as of 18-10-2004
|
||||
unsigned char EnablePageProgramming; // For JTAG parts only
|
||||
// Default TRUE
|
||||
unsigned char ucCacheType; // CacheType_Normal 0x00, CacheType_CAN 0x01, CacheType_HEIMDALL 0x02
|
||||
// New as of 27-10-2004
|
||||
unsigned char uiSramStartAddr[2]; // Start of SRAM
|
||||
unsigned char ucResetType; // Selects reset type, ResetNormal = 0x00, ResetAT76CXXX = 0x01
|
||||
unsigned char ucPCMaskExtended; // For parts with extended PC
|
||||
unsigned char ucPCMaskHigh; // PC high mask
|
||||
unsigned char ucEindAddress; // Selects reset type [EIND address...]
|
||||
// New as of early 2005, firmware 4.x
|
||||
unsigned char EECRAddress[2]; // EECR memory-mapped IO address
|
||||
};
|
||||
|
||||
/* New Xmega device descriptor, for firmware version 7 and above */
|
||||
// New Xmega device descriptor, for firmware version 7 and above
|
||||
struct xmega_device_desc {
|
||||
unsigned char whatever[2]; // cannot guess; must be 0x0002
|
||||
unsigned char datalen; // length of the following data, = 47
|
||||
unsigned char nvm_app_offset[4]; // NVM offset for application flash
|
||||
unsigned char nvm_boot_offset[4]; // NVM offset for boot flash
|
||||
unsigned char nvm_eeprom_offset[4]; // NVM offset for EEPROM
|
||||
unsigned char nvm_fuse_offset[4]; // NVM offset for fuses
|
||||
unsigned char nvm_lock_offset[4]; // NVM offset for lock bits
|
||||
unsigned char nvm_user_sig_offset[4]; // NVM offset for user signature row
|
||||
unsigned char nvm_prod_sig_offset[4]; // NVM offset for production sign. row
|
||||
unsigned char nvm_data_offset[4]; // NVM offset for data memory (SRAM + IO)
|
||||
unsigned char app_size[4]; // size of application flash
|
||||
unsigned char boot_size[2]; // size of boot flash
|
||||
unsigned char flash_page_size[2]; // flash page size
|
||||
unsigned char eeprom_size[2]; // size of EEPROM
|
||||
unsigned char eeprom_page_size; // EEPROM page size
|
||||
unsigned char nvm_base_addr[2]; // IO space base address of NVM controller
|
||||
unsigned char mcu_base_addr[2]; // IO space base address of MCU control
|
||||
unsigned char whatever[2]; // Cannot guess; must be 0x0002
|
||||
unsigned char datalen; // Length of the following data, = 47
|
||||
unsigned char nvm_app_offset[4]; // NVM offset for application flash
|
||||
unsigned char nvm_boot_offset[4]; // NVM offset for boot flash
|
||||
unsigned char nvm_eeprom_offset[4]; // NVM offset for EEPROM
|
||||
unsigned char nvm_fuse_offset[4]; // NVM offset for fuses
|
||||
unsigned char nvm_lock_offset[4]; // NVM offset for lock bits
|
||||
unsigned char nvm_user_sig_offset[4]; // NVM offset for user signature row
|
||||
unsigned char nvm_prod_sig_offset[4]; // NVM offset for production sign. row
|
||||
unsigned char nvm_data_offset[4]; // NVM offset for data memory (SRAM + IO)
|
||||
unsigned char app_size[4]; // Size of application flash
|
||||
unsigned char boot_size[2]; // Size of boot flash
|
||||
unsigned char flash_page_size[2]; // Flash page size
|
||||
unsigned char eeprom_size[2]; // Size of EEPROM
|
||||
unsigned char eeprom_page_size; // EEPROM page size
|
||||
unsigned char nvm_base_addr[2]; // IO space base address of NVM controller
|
||||
unsigned char mcu_base_addr[2]; // IO space base address of MCU control
|
||||
};
|
||||
#endif /* JTAGMKII_PRIVATE_EXPORTED */
|
||||
#endif // JTAGMKII_PRIVATE_EXPORTED
|
||||
|
||||
/* return code from jtagmkII_getsync() to indicate a "graceful"
|
||||
* failure, i.e. an attempt to enable ISP failed and should be
|
||||
|
||||
Reference in New Issue
Block a user