mirror of
https://github.com/avrdudes/avrdude.git
synced 2026-09-24 10:06:25 +03:00
Warn when opcodes have undefined results, eg, ld r26, X+
This commit is contained in:
Stefan Rueger
@@ -312,19 +312,19 @@ const AVR_opcode_data avr_opcodes[164] = {
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{OP_ID(ld_1), 0xfe0f, 0x900c, 1, OP_AVR2, "1001 000d dddd 1100", OTY_XFRX|OTY_RALL,
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"ld", "Rd, X", "Load Indirect", "Rd <-- (X)", "--------",
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{"2", "2", "2", "1/2"}, ""},
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{OP_ID(ld_2), 0xfe0f, 0x900d, 1, OP_AVR2, "1001 000d dddd 1101", OTY_XFRX|OTY_RALL,
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{OP_ID(ld_2), 0xfe0f, 0x900d, 1, OP_AVR2, "1001 000d dddd 1101", OTY_XFRX|OTY_RALL|OTY_XWRN,
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"ld", "Rd, X+", "Load Indirect and Post-Increment", "Rd <-- (X), X <-- X + 1", "--------",
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{"2", "2", "2", "2/3"}, ""},
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{OP_ID(ld_3), 0xfe0f, 0x900e, 1, OP_AVR2, "1001 000d dddd 1110", OTY_XFRX|OTY_RALL,
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{OP_ID(ld_3), 0xfe0f, 0x900e, 1, OP_AVR2, "1001 000d dddd 1110", OTY_XFRX|OTY_RALL|OTY_XWRN,
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"ld", "Rd, -X", "Load Indirect and Pre-Decrement", "X <-- X - 1, Rd <-- (X)", "--------",
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{"2", "3", "2", "2/3"}, ""},
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{OP_ID(ld_4), 0xfe0f, 0x8008, 1, OP_AVR2, "1000 000d dddd 1000", OTY_XFRX|OTY_RALL,
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"ld", "Rd, Y", "Load Indirect", "Rd <-- (Y) <-- (Y)", "--------",
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{"2", "2", "2", "1/2"}, "alias for ldd Rd, Y+0"},
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{OP_ID(ld_5), 0xfe0f, 0x9009, 1, OP_AVR2, "1001 000d dddd 1001", OTY_XFRX|OTY_RALL,
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{OP_ID(ld_5), 0xfe0f, 0x9009, 1, OP_AVR2, "1001 000d dddd 1001", OTY_XFRX|OTY_RALL|OTY_YWRN,
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"ld", "Rd, Y+", "Load Indirect and Post-Increment", "Rd <-- (Y), Y <-- Y + 1", "--------",
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{"2", "2", "2", "2/3"}, ""},
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{OP_ID(ld_6), 0xfe0f, 0x900a, 1, OP_AVR2, "1001 000d dddd 1010", OTY_XFRX|OTY_RALL,
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{OP_ID(ld_6), 0xfe0f, 0x900a, 1, OP_AVR2, "1001 000d dddd 1010", OTY_XFRX|OTY_RALL|OTY_YWRN,
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"ld", "Rd, -Y", "Load Indirect and Pre-Decrement", "Y <-- Y - 1 Rd <-- (Y)", "--------",
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{"2", "3", "2", "2/3"}, ""},
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{OP_ID(ldd_1), 0xd208, 0x8008, 1, OP_AVR2nRC, "10q0 qq0d dddd 1qqq", OTY_XFRX|OTY_RALL,
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@@ -333,10 +333,10 @@ const AVR_opcode_data avr_opcodes[164] = {
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{OP_ID(ld_7), 0xfe0f, 0x8000, 1, OP_AVR1, "1000 000d dddd 0000", OTY_XFRX|OTY_RALL,
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"ld", "Rd, Z", "Load Indirect", "Rd <-- (Z)", "--------",
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{"2", "2", "2", "1/2"}, "alias for ldd Rd, Z+0"},
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{OP_ID(ld_8), 0xfe0f, 0x9001, 1, OP_AVR1, "1001 000d dddd 0001", OTY_XFRX|OTY_RALL,
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{OP_ID(ld_8), 0xfe0f, 0x9001, 1, OP_AVR1, "1001 000d dddd 0001", OTY_XFRX|OTY_RALL|OTY_ZWRN,
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"ld", "Rd, Z+", "Load Indirect and Post-Increment", "Rd <-- (Z), Z <-- Z + 1", "--------",
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{"2", "2", "2", "2/3"}, ""},
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{OP_ID(ld_9), 0xfe0f, 0x9002, 1, OP_AVR1, "1001 000d dddd 0010", OTY_XFRX|OTY_RALL,
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{OP_ID(ld_9), 0xfe0f, 0x9002, 1, OP_AVR1, "1001 000d dddd 0010", OTY_XFRX|OTY_RALL|OTY_ZWRN,
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"ld", "Rd, -Z", "Load Indirect and Pre-Decrement", "Z <-- Z - 1, Rd <-- (Z)", "--------",
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{"2", "3", "2", "2/3"}, ""},
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{OP_ID(ldd_2), 0xd208, 0x8000, 1, OP_AVR2nRC, "10q0 qq0d dddd 0qqq", OTY_XFRX|OTY_RALL,
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@@ -348,19 +348,19 @@ const AVR_opcode_data avr_opcodes[164] = {
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{OP_ID(st_1), 0xfe0f, 0x920c, 1, OP_AVR2, "1001 001r rrrr 1100", OTY_XFRX|OTY_RALL,
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"st", "X, Rr", "Store Indirect", "(X) <-- Rr", "--------",
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{"2", "1", "1", "1"}, ""},
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{OP_ID(st_2), 0xfe0f, 0x920d, 1, OP_AVR2, "1001 001r rrrr 1101", OTY_XFRX|OTY_RALL,
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{OP_ID(st_2), 0xfe0f, 0x920d, 1, OP_AVR2, "1001 001r rrrr 1101", OTY_XFRX|OTY_RALL|OTY_XWRN,
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"st", "X+, Rr", "Store Indirect and Post-Increment", "(X) <-- Rr, X <-- X + 1", "--------",
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{"2", "1", "1", "1"}, ""},
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{OP_ID(st_3), 0xfe0f, 0x920e, 1, OP_AVR2, "1001 001r rrrr 1110", OTY_XFRX|OTY_RALL,
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{OP_ID(st_3), 0xfe0f, 0x920e, 1, OP_AVR2, "1001 001r rrrr 1110", OTY_XFRX|OTY_RALL|OTY_XWRN,
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"st", "-X, Rr", "Store Indirect and Pre-Decrement", "X <-- X - 1, (X) <-- Rr", "--------",
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{"2", "2", "1", "1"}, ""},
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{OP_ID(st_4), 0xfe0f, 0x8208, 1, OP_AVR2, "1000 001r rrrr 1000", OTY_XFRX|OTY_RALL,
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"st", "Y, Rr", "Store Indirect", "(Y) <-- Rr", "--------",
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{"2", "1", "1", "1"}, "alias for std Y+0, Rr"},
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{OP_ID(st_5), 0xfe0f, 0x9209, 1, OP_AVR2, "1001 001r rrrr 1001", OTY_XFRX|OTY_RALL,
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{OP_ID(st_5), 0xfe0f, 0x9209, 1, OP_AVR2, "1001 001r rrrr 1001", OTY_XFRX|OTY_RALL|OTY_YWRN,
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"st", "Y+, Rr", "Store Indirect and Post-Increment", "(Y) <-- Rr, Y <-- Y + 1", "--------",
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{"2", "1", "1", "1"}, ""},
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{OP_ID(st_6), 0xfe0f, 0x920a, 1, OP_AVR2, "1001 001r rrrr 1010", OTY_XFRX|OTY_RALL,
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{OP_ID(st_6), 0xfe0f, 0x920a, 1, OP_AVR2, "1001 001r rrrr 1010", OTY_XFRX|OTY_RALL|OTY_YWRN,
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"st", "-Y, Rr", "Store Indirect and Pre-Decrement", "Y <-- Y - 1, (Y) <-- Rr", "--------",
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{"2", "2", "1", "1"}, ""},
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{OP_ID(std_1), 0xd208, 0x8208, 1, OP_AVR2nRC, "10q0 qq1r rrrr 1qqq", OTY_XFRX|OTY_RALL,
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@@ -369,10 +369,10 @@ const AVR_opcode_data avr_opcodes[164] = {
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{OP_ID(st_7), 0xfe0f, 0x8200, 1, OP_AVR1, "1000 001r rrrr 0000", OTY_XFRX|OTY_RALL,
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"st", "Z, Rr", "Store Indirect", "(Z) <-- Rr", "--------",
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{"2", "1", "1", "1"}, "alias for std Z+0, Rr"},
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{OP_ID(st_8), 0xfe0f, 0x9201, 1, OP_AVR1, "1001 001r rrrr 0001", OTY_XFRX|OTY_RALL,
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{OP_ID(st_8), 0xfe0f, 0x9201, 1, OP_AVR1, "1001 001r rrrr 0001", OTY_XFRX|OTY_RALL|OTY_ZWRN,
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"st", "Z+, Rr", "Store Indirect and Post-Increment", "(Z) <-- Rr, Z <-- Z + 1", "--------",
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{"2", "1", "1", "1"}, ""},
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{OP_ID(st_9), 0xfe0f, 0x9202, 1, OP_AVR1, "1001 001r rrrr 0010", OTY_XFRX|OTY_RALL,
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{OP_ID(st_9), 0xfe0f, 0x9202, 1, OP_AVR1, "1001 001r rrrr 0010", OTY_XFRX|OTY_RALL|OTY_ZWRN,
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"st", "-Z, Rr", "Store Indirect and Pre-Decrement", "Z <-- Z - 1, (Z) <-- Rr", "--------",
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{"2", "2", "1", "1"}, ""},
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{OP_ID(std_2), 0xd208, 0x8200, 1, OP_AVR2nRC, "10q0 qq1r rrrr 0qqq", OTY_XFRX|OTY_RALL,
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@@ -384,7 +384,7 @@ const AVR_opcode_data avr_opcodes[164] = {
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{OP_ID(lpm_2), 0xfe0f, 0x9004, 1, OP_AVR25, "1001 000d dddd 0100", OTY_XFRX|OTY_RALL,
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"lpm", "Rd, Z", "Load Program Memory", "Rd <-- (Z)", "--------",
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{"3", "3", "3", "n/a"}, ""},
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{OP_ID(lpm_3), 0xfe0f, 0x9005, 1, OP_AVR25, "1001 000d dddd 0101", OTY_XFRX|OTY_RALL,
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{OP_ID(lpm_3), 0xfe0f, 0x9005, 1, OP_AVR25, "1001 000d dddd 0101", OTY_XFRX|OTY_RALL|OTY_ZWRN,
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"lpm", "Rd, Z+", "Load Program Memory and Post- Increment", "Rd <-- (Z), Z <-- Z + 1", "--------",
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{"3", "3", "3", "n/a"}, ""},
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{OP_ID(elpm_1), 0xffff, 0x95d8, 1, OP_AVR_L, "1001 0101 1101 1000", OTY_XFRX,
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@@ -393,7 +393,7 @@ const AVR_opcode_data avr_opcodes[164] = {
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{OP_ID(elpm_2), 0xfe0f, 0x9006, 1, OP_AVR_L, "1001 000d dddd 0110", OTY_XFRX|OTY_RALL,
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"elpm", "Rd, Z", "Extended Load Program Memory", "Rd <-- (RAMPZ:Z)", "--------",
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{"3", "3", "3", "n/a"}, ""},
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{OP_ID(elpm_3), 0xfe0f, 0x9007, 1, OP_AVR_L, "1001 000d dddd 0111", OTY_XFRX|OTY_RALL,
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{OP_ID(elpm_3), 0xfe0f, 0x9007, 1, OP_AVR_L, "1001 000d dddd 0111", OTY_XFRX|OTY_RALL|OTY_ZWRN,
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"elpm", "Rd, Z+", "Extended Load Program Memory and Post-Increment", "Rd <-- (RAMPZ:Z), Z <-- Z + 1", "--------",
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{"3", "3", "3", "n/a"}, ""},
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{OP_ID(spm), 0xffff, 0x95e8, 1, OP_AVR25, "1001 0101 1110 1000", OTY_XFRX,
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@@ -589,7 +589,7 @@ const AVR_opcode_data avr_opcodes[164] = {
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{"1-3", "1-3", "1-3", "1/2"}, ""},
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};
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// Return whether or not the giveb 16-bit opcode has a 16-bit address argument
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// Return whether or not the given 16-bit opcode has a 16-bit address argument
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int is_opcode32(int op) {
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return
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(op & 0xfe0e) == 0x940e || // call
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34
src/disasm.c
34
src/disasm.c
@@ -152,7 +152,7 @@ void disassemble(const char *buf, int addr, int opcode, AVR_opcode mnemo, Disasm
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// Apply register formula
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int regword = 0;
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switch(oc->type & OTY_RMASK) {
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switch(oc->type & OTY_REG_MASK) {
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case OTY_REVN: // Even registers r0, r2, ..., r30
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Rd *= 2, Rr *= 2;
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regword = 1; // movw
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@@ -175,6 +175,27 @@ void disassemble(const char *buf, int addr, int opcode, AVR_opcode mnemo, Disasm
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Ra = (Ra & 0xf) | ((Ra >> 1) & 0x30) | ((Ra & 0x10) << 2) | (((Ra & 0x10) ^ 0x10) << 3);
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}
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int awd = cx->dis_addrwidth, swd = cx->dis_sramwidth;
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snprintf(line->code, 256, "%-7s ", oc->opcode);
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char *c = line->code + strlen(line->code);
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*line->comment = 0;
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// Check for opcodes with undefined results
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switch(oc->type & OTY_WARN_MASK) {
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case OTY_XWRN:
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if(Rd == 26 || Rd == 27 || Rr == 26 || Rr == 27)
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add_comment(line, "Warning: the result of this operation is undefined\n");
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break;
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case OTY_YWRN:
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if(Rd == 28 || Rd == 29 || Rr == 28 || Rr == 29)
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add_comment(line, "Warning: the result of this operation is undefined\n");
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break;
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case OTY_ZWRN:
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if(Rd == 30 || Rd == 31 || Rr == 30 || Rr == 31)
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add_comment(line, "Warning: the result of this operation is undefined\n");
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break;
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}
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int target = 0, offset = 0, is_jumpcall = 0, is_relative = 0;
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int is_function = !!(oc->type & OTY_EXTERNAL); // call/rcall affects stack memory
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const char *kmemaddr = NULL, *memaddr, *regname;
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@@ -207,16 +228,8 @@ void disassemble(const char *buf, int addr, int opcode, AVR_opcode mnemo, Disasm
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Register_JumpCall(addr, target, mnemo, is_function);
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is_jumpcall = 1;
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break;
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default:
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pmsg_warning("OPCODE_%s has an unexpected number %d of k bits\n",
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oc->idname, Nk);
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}
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int awd = cx->dis_addrwidth, swd = cx->dis_sramwidth;
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snprintf(line->code, 256, "%-7s ", oc->opcode);
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char *c = line->code + strlen(line->code);
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*line->comment = 0;
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for(const char *o = oc->operands; *o && c-line->code < 255; o++) {
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switch(*o) {
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case 'R':
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@@ -370,8 +383,7 @@ int disasm(const char *buf, int buflen, int addr, int leadin, int leadout) {
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Pos += oplen;
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} else {
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term_out(".word 0x%02x%02x ; Invalid opcode at 0x%04x\n",
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buf[Pos + 1] & 0xff, buf[Pos] & 0xff, disasm_wrap(Pos + addr));
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term_out(".word 0x%02x%02x ; Invalid opcode\n", buf[Pos+1] & 0xff, buf[Pos] & 0xff);
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Pos += 2;
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}
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}
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@@ -1583,30 +1583,38 @@ typedef enum {
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#define PART_ALL (PART_AVR_XM|OP_AVR_L|OP_AVR_XL) // All but RC (the latter conflicts)
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// Opcode types
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#define OTY_RMASK 7 // Register formula mask
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#define OTY_REG_MASK 7 // Register formula mask
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#define OTY_RNONE 0 // No registers addressed in this opcode
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#define OTY_RALL 1 // Opcode can use all 32 registers (both Rd, Rr)
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#define OTY_REVN 2 // Opcode only uses even registers (Rd *= 2, Rr *= 2)
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#define OTY_RUPP 3 // Opcode only uses upper registers (Rd += 16, Rr += 16)
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#define OTY_RW24 4 // Opcode only uses r24, r26, r28, r30 (Rd = Rd *2 + 24)
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#define OTY_EXTERNAL 0x010 // Opcode might r/w either I/O region or memory
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#define OTY_ALBI 0x020 // Arithmetic, logic or bitwise operation
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#define OTY_ALBX 0x030 // Arithmetic, logic or bitwise operation (external)
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#define OTY_XFRI 0x040 // Data transfer (only affecting registers)
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#define OTY_XFRX 0x050 // Data transfer (between external I/O or memory and regs)
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#define OTY_JMPI 0x080 // Jump to potentially anywhere in flash (jmp, ijmp, eijmp)
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#define OTY_JMPX 0x090 // Jump to potentially anywhere in flash (calls and ret/i)
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#define OTY_RJMI 0x100 // Relative jump rjmp, range [-4094, 4096] bytes
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#define OTY_RJMX 0x110 // Relative call rcall, range [-4094, 4096] bytes
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#define OTY_BRAI 0x200 // Conditional branch, range [-126, 128] bytes
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#define OTY_SKPI 0x400 // Conditional skip, range [0, 4] bytes (cpse, sbrc, sbrs)
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#define OTY_SKPX 0x410 // Conditional skip, range [0, 4] bytes (sbic, sbis)
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#define OTY_MCUI 0x800 // nop and wdr
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#define OTY_MCUX 0x810 // sleep and break
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#define OTY_EXTERNAL 0x008 // Opcode might r/w either I/O region or memory
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#define OTY_ALIAS 0x1000 // Opcode is a strict alias for another one, eg, sbr == ori
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#define OTY_CONSTRAINT 0x2000 // Opcode has constraints: Rr == Rd (tst, clr, lsl, rol)
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#define OTY_TYPE_MASK 0x78 // OPCODE type mask
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#define OTY_ITYPE_MASK 0x70 // OPCODE type mask matching OTY_xxxI types
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#define OTY_MCUI 0x00 // nop and wdr
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#define OTY_MCUX 0x08 // sleep and break
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#define OTY_ALBI 0x10 // Arithmetic, logic or bitwise operation
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#define OTY_ALBX 0x18 // Arithmetic, logic or bitwise operation (external)
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#define OTY_XFRI 0x20 // Data transfer (only affecting registers)
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#define OTY_XFRX 0x28 // Data transfer (between external I/O or memory and regs)
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#define OTY_JMPI 0x30 // Jump to potentially anywhere in flash (jmp, ijmp, eijmp)
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#define OTY_JMPX 0x38 // Jump to potentially anywhere in flash (calls and ret/i)
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#define OTY_RJMI 0x40 // Relative jump rjmp, range [-4094, 4096] bytes
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#define OTY_RJMX 0x48 // Relative call rcall, range [-4094, 4096] bytes
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#define OTY_BRAI 0x50 // Conditional branch, range [-126, 128] bytes
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#define OTY_SKPI 0x60 // Conditional skip, range [0, 4] bytes (cpse, sbrc, sbrs)
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#define OTY_SKPX 0x68 // Conditional skip, range [0, 4] bytes (sbic, sbis)
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#define OTY_ALIAS 0x100 // Opcode is a strict alias for another one, eg, sbr == ori
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#define OTY_CONSTRAINT 0x200 // Opcode has constraints: Rr == Rd (tst, clr, lsl, rol)
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#define OTY_WARN_MASK 0xc00 // OPCODE warning mask
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#define OTY_XWRN 0x400 // Operand register must not be r27/r28
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#define OTY_YWRN 0x800 // Operand register must not be r29/r30
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#define OTY_ZWRN 0xc00 // Operand register must not be r29/r30
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typedef struct {
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AVR_opcode mnemo; // Eg, OPCODE_add
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