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rk3288: ddr: update ddr bin to DDR 20240527 fwver: v1.12

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build in:
	c9991c2 rk3288: update DDR 20240527 fwver: v1.12

update feature:
	30829bb rk3288: ddr fix 194MHz DQ/DQS phase not suitable
	10b27fc project: move project to Arm Development Studio IDE

Signed-off-by: Zhihuan He <huan.he@rock-chips.com>
Change-Id: I0c5b8fe4f77a1568c2672a053e2ab1702bf56076
This commit is contained in:
Zhihuan He
2024-05-27 14:07:50 +08:00
committed by Jianhong Chen
parent 7e38d7bccd
commit 030c9f9e0d
6 changed files with 34 additions and 6 deletions
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6
RKBOOT/RK3288.ini
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@@ -5,7 +5,7 @@ MAJOR=2
MINOR=58
[CODE471_OPTION]
NUM=1
Path1=bin/rk32/rk3288_ddr_400MHz_v1.11.bin
Path1=bin/rk32/rk3288_ddr_400MHz_v1.12.bin
Sleep=1
[CODE472_OPTION]
NUM=1
@@ -14,7 +14,7 @@ Path1=bin/rk32/rk3288_usbplug_v2.63.bin
NUM=2
LOADER1=FlashData
LOADER2=FlashBoot
FlashData=bin/rk32/rk3288_ddr_400MHz_v1.11.bin
FlashData=bin/rk32/rk3288_ddr_400MHz_v1.12.bin
FlashBoot=u-boot.bin
[OUTPUT]
PATH=rk3288_ubootloader_v1.11.bin
PATH=rk3288_ubootloader_v1.12.bin

6
RKBOOT/RK3288MINIALL.ini
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@@ -5,7 +5,7 @@ MAJOR=2
MINOR=58
[CODE471_OPTION]
NUM=1
Path1=bin/rk32/rk3288_ddr_400MHz_v1.11.bin
Path1=bin/rk32/rk3288_ddr_400MHz_v1.12.bin
Sleep=1
[CODE472_OPTION]
NUM=1
@@ -14,7 +14,7 @@ Path1=bin/rk32/rk3288_usbplug_v2.63.bin
NUM=2
LOADER1=FlashData
LOADER2=FlashBoot
FlashData=bin/rk32/rk3288_ddr_400MHz_v1.11.bin
FlashData=bin/rk32/rk3288_ddr_400MHz_v1.12.bin
FlashBoot=bin/rk32/rk3288_miniloader_v2.63.bin
[OUTPUT]
PATH=rk3288_loader_v1.10.263.bin
PATH=rk3288_loader_v1.12.263.bin

BIN
bin/rk32/rk3288_ddr_400MHz_v1.11.bin
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BIN
bin/rk32/rk3288_ddr_400MHz_v1.12.bin Normal file
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14
doc/release/RK3288_CN.md
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@@ -1,5 +1,19 @@
# RK3288 Release Note
## rk3288_ddr_400MHz_v1.12.bin
| 时间 | 文件 | 编译 commit | 重要程度 |
| ---------- | --------------------------- | ----------- | -------- |
| 2024-05-27 | rk3288_ddr_400MHz_v1.12.bin | c9991c2 | 紧急 |
### Fixed
| Index | 重要程度 | 更新说明 | 问题现象 | 问题来源 |
| ----- | -------- | -------------------------- | ----------------------------------- | -------- |
| 1 | 紧急 | 提高DDR 194MHz频点的稳定性 | 修复DDR在194MHz可能存在不稳定的现象 | |
------
## rk3288_tee_ta_v2.03.bin
| 时间 | 文件 | 编译 commit | 重要程度 |

14
doc/release/RK3288_EN.md
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@@ -1,5 +1,19 @@
# RK3288 Release Note
## rk3288_ddr_400MHz_v1.12.bin
| Date | File | Build commit | Severity |
| ---------- | --------------------------- | ------------ | -------- |
| 2024-05-27 | rk3288_ddr_400MHz_v1.12.bin | c9991c2 | critical |
### Fixed
| Index | Severity | Update | Issue description | Issue source |
| ----- | -------- | ------------------------ | ---------------------------------------------- | ------------ |
| 1 | critical | Fix DDR 194Mhz unstable. | The DDR run in 194Mhz may be data instability. | |
------
## rk3288_tee_ta_v2.03.bin
| Date | File | Build commit | Severity |