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rk3308: ddr: add initial version v1.11

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        7b62dfc rk3308: DDR Version V1.11
add
	1.set vpll0 in 1179.648MHz,vpll1 in 903.168MHz
	2.ddr in vpll0,set 589MHz
	3.adjusted deskew for aligning DQS and CK
	4.delete clk 50% duty ratio setting in cru
	5.set APLL,DPLL,VPLL0,VPLL1 without level shift
	6.set pll vco high,but lower 3.2GHz,for minimum jitter.
	7.add ddr scramble,include enable pmu pvtm.
	8.updata ddr config grf_os_reg2,grf_os_reg3 to v1.08.

Change-Id: Ia459f53d7d9623f3af7e0de1edc2f99735d57c80
Signed-off-by: Zhihuan He <huan.he@rock-chips.com>
This commit is contained in:
Zhihuan He
2018-04-13 21:02:42 +08:00
committed by Kever Yang
parent 53eab01b92
commit 3d6d644b7a
2 changed files with 20 additions and 0 deletions
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20
RKBOOT/RK3308MINIALL.ini Executable file
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[CHIP_NAME]
NAME=RK3308
[VERSION]
MAJOR=1
MINOR=01
[CODE471_OPTION]
NUM=1
Path1=bin/rk33/rk3308_ddr_589MHz_v1.11.bin
Sleep=1
[CODE472_OPTION]
NUM=1
Path1=bin/rk33/rk3308_usbplug_v1.01.bin
[LOADER_OPTION]
NUM=2
LOADER1=FlashData
LOADER2=FlashBoot
FlashData=bin/rk33/rk3308_ddr_589MHz_v1.11.bin
FlashBoot=bin/rk33/rk3308_miniloader_v1.01.bin
[OUTPUT]
PATH=rk3308_loader_v1.11.101.bin

BIN
bin/rk33/rk3308_ddr_589MHz_v1.11.bin Executable file
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