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tool: ddrbin_tool: update to v1.07 20210603

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1.add modify driver strength, odt, Vref and etc for rv1126 and rk3568
2.support getting ddrbin config to gen_param.txt:
    ./ddrbin_tool -g gen_param.txt px30_ddr_333MHz_v1.15.bin
3.add disable print training.

Signed-off-by: Zhihuan He <huan.he@rock-chips.com>
Change-Id: I8c101dacd14926891d1632095fa9e1af1ab4f286
This commit is contained in:
Zhihuan He
2021-05-10 09:12:25 +08:00
committed by Jianhong Chen
parent 3fce1f759e
commit 862514293b
3 changed files with 410 additions and 30 deletions
Download Patch File Download Diff File Expand all files Collapse all files

194
tools/ddrbin_param.txt
View File

@@ -1,3 +1,4 @@
/* Please get help from ddrbin_tool_user_guide.txt and './ddrbin_tool -h' */
start tag=0x12345678
ddr2_freq=
lp2_freq=
@@ -11,6 +12,16 @@ uart id=
uart iomux=
uart baudrate=
sr_idle=
pd_idle=
first scan channel=
channel mask=
stride type=
standby_idle=
dis_printf_training=
ssmod_downspread=
ssmod_div=
ssmod_spread=
@@ -22,41 +33,224 @@ ddr2_f2_freq_mhz=
ddr2_f3_freq_mhz=
ddr2_f4_freq_mhz=
ddr2_f5_freq_mhz=
phy_ddr2_dq_drv_when_odten_ohm=
phy_ddr2_ca_drv_when_odten_ohm=
phy_ddr2_clk_drv_when_odten_ohm=
ddr2_dq_drv_when_odten_ohm=
phy_ddr2_dq_drv_when_odtoff_ohm=
phy_ddr2_ca_drv_when_odtoff_ohm=
phy_ddr2_clk_drv_when_odtoff_ohm=
ddr2_dq_drv_when_odtoff_ohm=
phy_ddr2_odt_ohm=
ddr2_odt_ohm=
phy_ddr2_odt_pull_up_en=
phy_ddr2_odt_pull_dn_en=
phy_ddr2_odten_freq_mhz=
ddr2_odten_freq_mhz=
phy_ddr2_dq_sr_when_odten=
phy_ddr2_ca_sr_when_odten=
phy_ddr2_clk_sr_when_odten=
phy_ddr2_dq_sr_when_odtoff=
phy_ddr2_ca_sr_when_odtoff=
phy_ddr2_clk_sr_when_odtoff=
ddr3_f1_freq_mhz=
ddr3_f2_freq_mhz=
ddr3_f3_freq_mhz=
ddr3_f4_freq_mhz=
ddr3_f5_freq_mhz=
phy_ddr3_dq_drv_when_odten_ohm=
phy_ddr3_ca_drv_when_odten_ohm=
phy_ddr3_clk_drv_when_odten_ohm=
ddr3_dq_drv_when_odten_ohm=
phy_ddr3_dq_drv_when_odtoff_ohm=
phy_ddr3_ca_drv_when_odtoff_ohm=
phy_ddr3_clk_drv_when_odtoff_ohm=
ddr3_dq_drv_when_odtoff_ohm=
phy_ddr3_odt_ohm=
ddr3_odt_ohm=
phy_ddr3_odt_pull_up_en=
phy_ddr3_odt_pull_dn_en=
phy_ddr3_odten_freq_mhz=
ddr3_odten_freq_mhz=
phy_ddr3_dq_sr_when_odten=
phy_ddr3_ca_sr_when_odten=
phy_ddr3_clk_sr_when_odten=
phy_ddr3_dq_sr_when_odtoff=
phy_ddr3_ca_sr_when_odtoff=
phy_ddr3_clk_sr_when_odtoff=
ddr4_f1_freq_mhz=
ddr4_f2_freq_mhz=
ddr4_f3_freq_mhz=
ddr4_f4_freq_mhz=
ddr4_f5_freq_mhz=
phy_ddr4_dq_drv_when_odten_ohm=
phy_ddr4_ca_drv_when_odten_ohm=
phy_ddr4_clk_drv_when_odten_ohm=
ddr4_dq_drv_when_odten_ohm=
phy_ddr4_dq_drv_when_odtoff_ohm=
phy_ddr4_ca_drv_when_odtoff_ohm=
phy_ddr4_clk_drv_when_odtoff_ohm=
ddr4_dq_drv_when_odtoff_ohm=
phy_ddr4_odt_ohm=
ddr4_odt_ohm=
phy_ddr4_odt_pull_up_en=
phy_ddr4_odt_pull_dn_en=
phy_ddr4_odten_freq_mhz=
ddr4_odten_freq_mhz=
phy_ddr4_dq_sr_when_odten=
phy_ddr4_ca_sr_when_odten=
phy_ddr4_clk_sr_when_odten=
phy_ddr4_dq_sr_when_odtoff=
phy_ddr4_ca_sr_when_odtoff=
phy_ddr4_clk_sr_when_odtoff=
lp2_f1_freq_mhz=
lp2_f2_freq_mhz=
lp2_f3_freq_mhz=
lp2_f4_freq_mhz=
lp2_f5_freq_mhz=
phy_lp2_dq_drv_when_odten_ohm=
phy_lp2_ca_drv_when_odten_ohm=
phy_lp2_clk_drv_when_odten_ohm=
lp2_dq_drv_when_odten_ohm=
phy_lp2_dq_drv_when_odtoff_ohm=
phy_lp2_ca_drv_when_odtoff_ohm=
phy_lp2_clk_drv_when_odtoff_ohm=
lp2_dq_drv_when_odtoff_ohm=
phy_lp2_odt_ohm=
lp2_odt_ohm=
phy_lp2_odt_pull_up_en=
phy_lp2_odt_pull_dn_en=
phy_lp2_odten_freq_mhz=
lp2_odten_freq_mhz=
phy_lp2_dq_sr_when_odten=
phy_lp2_ca_sr_when_odten=
phy_lp2_clk_sr_when_odten=
phy_lp2_dq_sr_when_odtoff=
phy_lp2_ca_sr_when_odtoff=
phy_lp2_clk_sr_when_odtoff=
lp3_f1_freq_mhz=
lp3_f2_freq_mhz=
lp3_f3_freq_mhz=
lp3_f4_freq_mhz=
lp3_f5_freq_mhz=
phy_lp3_dq_drv_when_odten_ohm=
phy_lp3_ca_drv_when_odten_ohm=
phy_lp3_clk_drv_when_odten_ohm=
lp3_dq_drv_when_odten_ohm=
phy_lp3_dq_drv_when_odtoff_ohm=
phy_lp3_ca_drv_when_odtoff_ohm=
phy_lp3_clk_drv_when_odtoff_ohm=
lp3_dq_drv_when_odtoff_ohm=
phy_lp3_odt_ohm=
lp3_odt_ohm=
phy_lp3_odt_pull_up_en=
phy_lp3_odt_pull_dn_en=
phy_lp3_odten_freq_mhz=
lp3_odten_freq_mhz=
phy_lp3_dq_sr_when_odten=
phy_lp3_ca_sr_when_odten=
phy_lp3_clk_sr_when_odten=
phy_lp3_dq_sr_when_odtoff=
phy_lp3_ca_sr_when_odtoff=
phy_lp3_clk_sr_when_odtoff=
lp4_f1_freq_mhz=
lp4_f2_freq_mhz=
lp4_f3_freq_mhz=
lp4_f4_freq_mhz=
lp4_f5_freq_mhz=
phy_lp4_dq_drv_when_odten_ohm=
phy_lp4_ca_drv_when_odten_ohm=
phy_lp4_clk_drv_when_odten_ohm=
lp4_dq_drv_when_odten_ohm=
phy_lp4_dq_drv_when_odtoff_ohm=
phy_lp4_ca_drv_when_odtoff_ohm=
phy_lp4_clk_drv_when_odtoff_ohm=
lp4_dq_drv_when_odtoff_ohm=
phy_lp4_odt_ohm=
lp4_odt_ohm=
lp4_ca_odt_ohm=
lp4_drv_pu_cal_odten=
lp4_drv_pu_cal_odtoff=
phy_lp4_drv_pull_dn_en_odten=
phy_lp4_drv_pull_dn_en_odtoff=
phy_lp4_odten_freq_mhz=
lp4_dq_odten_freq_mhz=
phy_lp4_dq_sr_when_odten=
phy_lp4_ca_sr_when_odten=
phy_lp4_clk_sr_when_odten=
phy_lp4_dq_sr_when_odtoff=
phy_lp4_ca_sr_when_odtoff=
phy_lp4_clk_sr_when_odtoff=
lp4_ca_odten_freq_mhz=
phy_lp4_cs_drv_odten=
phy_lp4_cs_drv_odtoff=
lp4_odte_ck=
lp4_odte_cs_en=
lp4_odtd_ca_en=
phy_lp4_dq_vref_when_odten=
lp4_dq_vref_when_odten=
lp4_ca_vref_when_odten=
phy_lp4_dq_vref_when_odtoff=
lp4_dq_vref_when_odtoff=
lp4_ca_vref_when_odtoff=
ddr2_bytes_map=
ddr3_bytes_map=
ddr4_bytes_map=
lp2_bytes_map=
lp3_bytes_map=
lp4_bytes_map=
lp3_dq0_7_map=
lp2_dq0_7_map=
ddr4_cs0_dq0_dq15_map=
ddr4_cs0_dq16_dq31_map=
ddr4_cs1_dq0_dq15_map=
ddr4_cs1_dq16_dq31_map=
lp4x_f1_freq_mhz=
lp4x_f2_freq_mhz=
lp4x_f3_freq_mhz=
lp4x_f4_freq_mhz=
lp4x_f5_freq_mhz=
phy_lp4x_dq_drv_when_odten_ohm=
phy_lp4x_ca_drv_when_odten_ohm=
phy_lp4x_clk_drv_when_odten_ohm=
lp4x_dq_drv_when_odten_ohm=
phy_lp4x_dq_drv_when_odtoff_ohm=
phy_lp4x_ca_drv_when_odtoff_ohm=
phy_lp4x_clk_drv_when_odtoff_ohm=
lp4x_dq_drv_when_odtoff_ohm=
phy_lp4x_odt_ohm=
lp4x_odt_ohm=
lp4x_ca_odt_ohm=
lp4x_drv_pu_cal_odten=
lp4x_drv_pu_cal_odtoff=
phy_lp4x_drv_pull_dn_en_odten=
phy_lp4x_drv_pull_dn_en_odtoff=
phy_lp4x_odten_freq_mhz=
lp4x_dq_odten_freq_mhz=
phy_lp4x_dq_sr_when_odten=
phy_lp4x_ca_sr_when_odten=
phy_lp4x_clk_sr_when_odten=
phy_lp4x_dq_sr_when_odtoff=
phy_lp4x_ca_sr_when_odtoff=
phy_lp4x_clk_sr_when_odtoff=
lp4x_ca_odten_freq_mhz=
phy_lp4x_cs_drv_odten=
phy_lp4x_cs_drv_odtoff=
lp4x_odte_ck=
lp4x_odte_cs_en=
lp4x_odtd_ca_en=
phy_lp4x_dq_vref_when_odten=
lp4x_dq_vref_when_odten=
lp4x_ca_vref_when_odten=
phy_lp4x_dq_vref_when_odtoff=
lp4x_dq_vref_when_odtoff=
lp4x_ca_vref_when_odtoff=
end

BIN
tools/ddrbin_tool
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Binary file not shown.

246
tools/ddrbin_tool_user_guide.txt
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@@ -1,23 +1,66 @@
1. modify "ddrbin_param.txt", choose ddr frequency, uart info.
2. run "ddrbin_tool" with argument 1: ddrbin_param.txt, argument 2: ddr bin file.
like: ./ddrbin_tool ddrbin_param.txt px30_ddr_333MHz_v1.13.bin
function 1: modify ddr.bin file from ddrbin_param.txt.
1) modify "ddrbin_param.txt", set ddr frequency, uart info etc what you want.
If want to keep items default, please keep these items blank.
2) run "ddrbin_tool" with argument 1: ddrbin_param.txt, argument 2: ddr bin file.
like: ./ddrbin_tool ddrbin_param.txt px30_ddr_333MHz_v1.13.bin
function 2: get ddr.bin file config to gen_param.txt file
If want to get ddrbin file config, please run like that:
./ddrbin_tool -g gen_param.txt px30_ddr_333MHz_v1.15.bin
The config will show in gen_param.txt.
support following chip:
PX30: ddr bin version should be released later than V1.11. Support modify uart info only. The ddr bin version V1.12 and later support DDR 2t info modification, only DDR3 support. The ddr bin version V1.16 and later support ssmod.
RK1808: ddr bin version should be released later than V1.03. Support modify uart info and ddr frequency. ddr freq should be one of 333,400,533,666,786,933. The ddr bin version V1.03 and later support DDR 2t info modification, only DDR2/DDR3/DDR4 support. The ddr bin version V1.05 and later support ssmod.
RK322x: ddr bin version should be released later than V1.08. Support modify uart info and ddr frequency. These is no limit to ddr frequency. The ddr bin version V1.09 and later support DDR 2t info modification, only DDR2/DDR3 support.
RK322xh: ddr bin version should be released later than V1.14. Support modify uart info only. The ddr bin version V1.16 and later support DDR 2t info modification, only DDR3 support. The ddr bin version V1.17 and later support ssmod.
RK3288: ddr bin version should be released later than V1.07. Support modify uart info only. The ddr bin version V1.08 and later support DDR 2t info modification, only DDR3 support.
RK3308: ddr bin version should be released later than V1.28. Support modify uart info and ddr frequency. ddr freq should be one of 393,451,589. The ddr bin version V1.29 and later support DDR 2t info modification, only DDR2/DDR3 support. The ddr bin version V1.31 and later support ssmod.
RK3326: ddr bin version should be released later than V1.11. Support modify uart info only. The ddr bin version V1.12 and later support DDR 2t info modification, only DDR3 support. The ddr bin version V1.16 and later support ssmod.
RK3368: ddr bin version should be released later than V2.04. Support modify uart info and ddr frequency. These is no limit to ddr frequency. The ddr bin version V2.05 and later support DDR 2t info modification, only DDR3 support.
RK3328: ddr bin version should be released later than V1.14. Support modify uart info only. The ddr bin version V1.16 and later support DDR 2t info modification, only DDR3 support. The ddr bin version V1.17 and later support ssmod.
RK3399: ddr bin version should be released later than V1.25. Support modify uart info only. The ddr bin version V1.25 and later support ssmod.
RK3399PRO NPU: ddr bin version should be released later than V1.03. Support modify uart info and ddr frequency. ddr freq should be one of 333,400,533,666,786,933. The ddr bin version V1.03 and later support DDR 2t info modification, only DDR2/DDR3/DDR4 support. The ddr bin version V1.05 and later support ssmod.
RV1126/RV1109: all of version. Support modify uart info and ddr frequency. ddr freq should be one of 330,396,528,664,784,924,1056. Support DDR 2t info modification, only DDR3/DDR4 support. The ddr bin version V1.05 and later support ssmod.
The detail information as following:
* support ddrbin version
The 'X' means not support change those parameters by tool.
+---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+
| platform | uart info | ddr freq | ssmod | DDR 2T | sr pd | drv, odt, Vref etc| dis print training info | dis CBT |
+---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+
| RV1108 | V1.08 | V1.08 | V1.10 | V1.08 | V1.08 | X | X | X |
+---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+
| PX30/RK3326 | V1.11 | X | V1.16 | V1.12 | V1.15 | X | X | X |
+---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+
| RK1808 | V1.03 | V1.03 | V1.05 | V1.03 | V1.04 | X | X | X |
+---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+
| RK322x | V1.08 | V1.08 | X | V1.09 | X | X | X | X |
+---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+
| RK322xh | V1.14 | X | V1.17 | V1.16 | V1.17 | X | X | X |
+---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+
| RK3288 | V1.07 | X | X | V1.08 | X | X | X | X |
+---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+
| RK3308 | V1.28 | V1.28 | V1.31 | V1.29 | V1.30 | X | X | X |
+---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+
| RK3368 | V2.04 | V2.04 | X | V2.05 | X | X | X | X |
+---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+
| RK3328 | V1.14 | X | V1.17 | V1.16 | V1.17 | X | X | X |
+---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+
| RK3399 | V1.25 | X | V1.25 | X | X | X | X | X |
+---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+
| RK3399PRO NPU | V1.03 | V1.03 | X | V1.03 | X | X | X | X |
+---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+
| RV1126/RV1109 | V1.00 | V1.00 | V1.05 | V1.00 | V1.05 | V1.05 | X | X |
+---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+
| RK3566/RK3568 | V1.00 | V1.00 | V1.06 | V1.00 | V1.00 | V1.06 | V1.07 | X |
+---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+
* UART info
uart id: uart number. 0 for uart0, 1 for uart1, 2 for uart2..., 0xf will disable uart.
uart iomux: uart iomux info, 0 for uartn_m0, 1 for uartn_m1, 2 for uartn_m2...(like uart2_m0, uart2_m1,uart2_m2),
or 1 for uartn_a, 2 for uartn_b, 3 for uartn_c.(like uar2a, uart2b, uart2c).
uart baudrate: uart baudrate should be 115200 or 1500000.
* disable print training information
dis_printf_training: 1: will disabled print training information; 0: will enable print training information.
* disable Command Bus Training(CBT) for lp4/lp4x
dis_cbt_for_lp4_lp4x: 1: will disbaled CBT for lp4/lp4x; 0: will enable CBT for lp4/lp4x. Reserve function, all platforms are not support.
* DDR (final) freq
For RV1126/RV1109, RK3566/RK3568, the frequencies as follows can choose to final freq in loader.
ddrbin_param.txt:
start tag: keep default value. Do not modify it.
ddr2_freq: ddr2 frequency, unit:MHz.
lp2_freq: lpddr2 frequency, unit:MHz.
ddr3_freq: ddr3 frequency, unit:MHz.
@@ -26,17 +69,38 @@ ddr4_freq: ddr4 frequency, unit:MHz.
lp4_freq: lpddr4 frequency, unit:MHz.
lp4x_freq: lpddr4x frequency, unit:MHz.
If ddr*_freq/lp*_freq is no value, it's frequency will keep the same with the ddr bin frequency.
The 'X' as follows means not support change frequencies by tool.
+---------------+-----------------------------------------------------------------+
| platform | support frequencies |
+---------------+-----------------------------------------------------------------+
| RK1108 | DDR2 fix 400, LP2 not larger than 533, DDR3 not larger than 800 |
+---------------+-----------------------------------------------------------------+
| PX30/RK3326 | X |
+---------------+-----------------------------------------------------------------+
| RK1808 | 333,400,533,666,786,933 |
+---------------+-----------------------------------------------------------------+
| RK322x | DDR2/LP2 not larger than 533, not larger than 800 |
+---------------+-----------------------------------------------------------------+
| RK322xh | X |
+---------------+-----------------------------------------------------------------+
| RK3288 | X |
+---------------+-----------------------------------------------------------------+
| RK3308 | 393,451,589 |
+---------------+-----------------------------------------------------------------+
| RK3368 | DDR3 not larger than 800, LP3 not larger than 666 |
+---------------+-----------------------------------------------------------------+
| RK3328 | X |
+---------------+-----------------------------------------------------------------+
| RK3399 | X |
+---------------+-----------------------------------------------------------------+
| RK3399PRO NPU | 333,400,533,666,786,933 |
+---------------+-----------------------------------------------------------------+
| RV1126/RV1109 | 328,396,528,664,784,924,1056 |
+---------------+-----------------------------------------------------------------+
| RK3566/RK3568 | 324,396,528,630,780,920,1056,1184,1332,1560 |
+---------------+-----------------------------------------------------------------+
uart id: uart number. 0 for uart0, 1 for uart1, 2 for uart2..., 0xf will disable uart.
uart iomux: uart iomux info, 0 for uartn_m0, 1 for uartn_m1, 2 for uartn_m2...(like uart2_m0, uart2_m1,uart2_m2),
Or 1 for uartn_a, 2 for uartn_b, 3 for uartn_c.(like uar2a, uart2b, uart2c).
uart baudrate: uart baudrate should be 115200 or 1500000.
If uart id/iomux/baudrate is no value, uart info will keep the same with ddr bin config.
ddr_2t: ddr 2T timing mode. 1: enable ddr 2T, 0: disable ddr 2T.
If 'ddr_2t' is no value, ddr_2t info will keep the same with ddr bin config.
* DDR frequencies(add more)
ddr2_f1_freq_mhz: ddr2 frequency number 1, unit:MHz.
ddr2_f2_freq_mhz: ddr2 frequency number 2, unit:MHz.
@@ -44,11 +108,133 @@ ddr2_f3_freq_mhz: ddr2 frequency number 3, unit:MHz.
ddr2_f4_freq_mhz: ddr2 frequency number 4, unit:MHz.
ddr2_f5_freq_mhz: ddr2 frequency number 5, unit:MHz.
...
ddr*_f*_freq_mhz/lp*_f*_freq_mhz: Only RV1126/RV1109 used.The program will initialize dram by following order for example: ddr4_freq, ddr4_f1_freq_mhz, ddr4_f2_freq_mhz, ddr4_f3_freq_mhz, ddr4_f4_freq_mhz, ddr4_f5_freq_mhz.
And the final frequency is ddr4_freq to boot system.
ddr*_f*_freq_mhz/lp*_f*_freq_mhz: Only RV1126/RV1109, RK3566/RK3568 used.The program will initialize dram by following order.
for example: ddr4_f1_freq_mhz --> ddr4_f2_freq_mhz --> ddr4_f3_freq_mhz --> ddr4_freq.
And the final frequency is 'ddr4_freq' to boot system.
So it is better to arrange the frequency values in order as above. That means the max freq is in final freq(lp*/ddr*_freq) and the min freq is in 'ddr*/lp*_f1_freq_mhz'.
ddr*/lp*_f1_freq_mhz < ddr*/lp*_f2_freq_mhz < ddr*/lp*_f3_freq_mhz < lp*/ddr*_freq(the final freq)
For example:
...
ddr4_freq=1560
...
ddr4_f1_freq_mhz=324
ddr4_f2_freq_mhz=528
ddr4_f3_freq_mhz=780
...
The ddr frequency table in kernel dts/dtsi file need correspond to these frequencies.
* SR PD idle
sr_idle: auto self-refresh mode delay time.
pd_idle: auto power-down mode delay time.
* DDR 2T
ddr_2t: ddr 2T timing mode. 1: enable ddr 2T, 0: disable ddr 2T.
* PLL ssmod
These parameters are about Spread Spectrum Modulator(ssmod) for PLL.
ssmod_downspread: ssmod work mode. 0: down spread, 1: center spread.
ssmod_div: Divider required to set the modulation frequency. RK3308 suggests to ssmod_div=2, others platforms suggest to ssmod_div=5.
ssmod_spread: spread amplitude % = 0.1 * ssmod_spread; 0: disable ssmod, others will enable ssmod, max to 0x1f.
* driver strength
phy_ddr*_dq_drv_when_odten_ohm: The PHY DQ/DQS driver strength(write direction) when DRAM odt on. unit: ohm.
phy_ddr*_ca_drv_when_odten_ohm: The PHY CMD/ADDR driver strength when DRAM odt on. unit: ohm.
phy_ddr*_clk_drv_when_odten_ohm: The PHY clock driver strength when DRAM odt on. unit: ohm.
ddr*_dq_drv_when_odten_ohm: The DRAM DQ/DQS driver strength(read direction) when PHY odt on. unit: ohm.
phy_ddr*_dq_drv_when_odtoff_ohm: The PHY DQ/DQS driver strength(write direction) when DRAM odt off. unit: ohm.
phy_ddr*_ca_drv_when_odtoff_ohm: The PHY CMD/ADDR driver strength when DRAM odt off. unit: ohm.
phy_ddr*_clk_drv_when_odtoff_ohm: The PHY clock driver strength when DRAM odt off. unit: ohm.
ddr*_dq_drv_when_odtoff_ohm: The DRAM DQ/DQS driver strength(read direction) when PHY odt off. unit: ohm.
The phy side driver strength support value as follows:
+---------------+-------------------+-------------------+--------------+-----------------+----------------+----------------+
| platform | DDR3 | DDR4 | LP3 | LP4 | LP4X pull up | LP4X pull down |
+---------------+-------------------+-------------------+--------------+-----------------+----------------+----------------+
| | 455,230,153,115, | 482,244,162,122, | | 501,253,168,126,| | |
| | 91,76,65,57,51,46,| 97,81,69,61,54,48,| | 101,84,72,63,56,| | |
| RV1126/RV1109 | 41,38,35,32,30,28,| 44,40,37,34,32,30,| follow DDR4 | 50,46,42,38,36, | follow LP4 | follow LP4 |
| | 27,25,24,23,22,21,| 28,27,25,24,23,22,| | 33,31,29,28,26, | | |
| | 20 | 21 | | 25,24,23,22 | | |
+---------------+-------------------+-------------------+--------------+-----------------+----------------+----------------+
| | 500,250,167,125, | 556,279,185,139, | | 576,289,192,144,| 646,323,215, | 513,259,172, |
| | 100,83,71,63,56, | 111,93,79,69,62, | | 115,96,82,72,64,| 162,129,108,92,| 130,104,86,74, |
| RK3566/RK3568 | 50,45,41,38,36,33,| 55,50,46,42,39,37,| follow DDR4 | 57,52,48,44,41, | 81,72,65,59,54,| 65,58,52,47,43,|
| | 31,29,28,26,25,24,| 34,32,31,29,27,26,| | 38,36,34,32,30, | 50,46,43,40,38,| 40,37,35,32,30,|
| | 23,22 | 25,24 | | 28,27,26,25 | 36,34,32,31,29,| 29,27,26,25,24,|
| | | | | | 28 | 23 |
+---------------+-------------------+-------------------+--------------+-----------------+----------------+----------------+
The DRAM side driver strength support value as follows:
+---------------+-------------------+-------------------+----------------+----------------------+----------------+
| platform | DDR3 | DDR4 | LP3 | LP4 | LP4X |
+---------------+-------------------+-------------------+----------------+----------------------+----------------+
| all | 40,34 | 34,48 | 34,40,48,60,80 | 40,48,60,80,120,240 | follow LP4 |
+---------------+-------------------+-------------------+----------------+----------------------+----------------+
* ODT
phy_ddr*_odt_ohm: The PHY ODT strength(read direction). unit: ohm.
ddr*_odt_ohm: The DRAM ODT strength(write direction). unit: ohm.
phy_ddr*_odt_pull_up_en: 1: enable PHY pull up odt. 0: disable
phy_ddr*_odt_pull_dn_en: 1: enable PHY pull down odt. 0: disable
phy_ddr*_odten_freq_mhz: The PHY odt enable when larger than this frequency. unit: MHz.
ddr*_odten_freq_mhz: The DRAM odt(DQ/DQS) enable when larger than this frequency. unit: MHz.
The phy side ODT support value as follows:
The ODT "0" means disabled ODT.
+---------------+-------------------+--------------------+--------------+-------------------+----------------+----------------+
| platform | DDR3 | DDR4 | LP3 | LP4 | LP4X pull up | LP4X pull down |
+---------------+-------------------+--------------------+--------------+-------------------+----------------+----------------+
| | 0,561,282,188,141,| 0,586,294,196,148, | | 0,604,303,202,152,| | |
| | 113,94,81,72,64, | 118,99,58,76,67,60,| | 122,101,87,78,69, | | |
| RV1126/RV1109 | 58,52,48,44,41, | 55,50,46,43,40,38, | follow DDR4 | 62,56,52,48,44,41,| follow LP4 | follow LP4 |
| | 38,37,34,32,31,29,| 36,34,32,31,29,28, | | 39,37,35,33,32,30,| | |
| | 28,27,25 | 27 | | 29,27 | | |
+---------------+-------------------+--------------------+--------------+-------------------+----------------+----------------+
| | 0,500,250,167,125,| 0,556,279,185,139, | | 0,576,289,192,144,| 0,646,323,215, | 0,513,259,172, |
| | 100,83,71,63,56, | 111,93,79,69,62, | | 115,96,82,72,64, | 162,129,108,92,| 130,104,86,74, |
| RK3566/RK3568 | 50,45,41,38,36,33,| 55,50,46,42,39,37, | follow DDR4 | 57,52,48,44,41, | 81,72,65,59,54,| 65,58,52,47,43,|
| | 31,29,28,26,25,24,| 34,32,31,29,27,26, | | 38,36,34,32,30, | 50,46,43,40,38,| 40,37,35,32,30,|
| | 23,22 | 25,24 | | 28,27,26,25 | 36,34,32,31,29,| 29,27,26,25,24,|
| | | | | | 28 | 23 |
+---------------+-------------------+--------------------+--------------+-------------------+----------------+----------------+
The DRAM side ODT support value as follows:
+---------------+-------------------+-------------------+--------------+-----------------------+----------------+
| platform | DDR3 | DDR4 | LP3 | LP4(include DQ and CA)| LP4X |
+---------------+-------------------+-------------------+--------------+-----------------------+----------------+
| all | 0,40,60,120 | 0,34,40,48,60,120 | 0,60,120,240 | 0,40,48,60,80,120,240 | follow LP4 |
+---------------+-------------------+-------------------+--------------+-----------------------+----------------+
* slew rate
phy_ddr*_dq_sr_when_odten: The PHY DQ/DQS slew rate when odt on.
phy_ddr*_ca_sr_when_odten: The PHY CMD/ADDR slew rate when odt on.
phy_ddr*_clk_sr_when_odten: The PHY clock slew rate when odt on.
phy_ddr*_dq_sr_when_odtoff: The PHY DQ/DQS slew rate when odt off.
phy_ddr*_ca_sr_when_odtoff: The PHY CMD/ADDR slew rate when odt off.
phy_ddr*_clk_sr_when_odtoff: The PHY clock slew rate when odt off.
* byte map
ddr*_bytes_map: Reserve function.
* dq remap
lp*_dq*_*_map: Reserve function.
ddr*_cs*_dq*_dq*_map: Reserve function.
* lp4/lp4x more information
lp4*_ca_odten_freq_mhz: The DRAM CMD/ADDR odt enable when larger than this frequency. unit: MHz.
phy_lp4*_dq_vref_when_odten: The PHY VrefDQ when PHY odt on. uint: parts per thousand.
lp4*_dq_vref_when_odten: The DRAM VrefDQ when DRAM DQ/DQS odt on. uint: parts per thousand.
lp4*_ca_vref_when_odten: The DRAM VrefCA when DRAM CA odt on. uint: parts per thousand.
phy_lp4_dq_vref_when_odtoff: The PHY VrefDQ when PHY odt off. uint: parts per thousand.
lp4_dq_vref_when_odtoff: The DRAM VrefDQ when DRAM DQ/DQS odt off. uint: parts per thousand.
lp4_ca_vref_when_odtoff: The DRAM VrefCA when DRAM CA odt off. uint: parts per thousand.