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rk3568: bl31: update version to v1.34

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Build from ATF commit:
    4613ae965 plat: rk3568: scmi clock: adjust pvtpll config for npu
update feature:
    4613ae965 plat: rk3568: scmi clock: adjust pvtpll config for npu
    7654298e1 plat: rk356x: dmc: Add automatic temperature derating for LPDDR4(X)
    33aaaa4f2 plat: rk3588: fix pd status error for some power domains
    3b212f222 plat: rk3588: sleep: support GPIO_POWER_CONFIG
    aeb1341f2 plat: rk3568: pmu_ultra: fix some emmc resume fail
    45c8fcb44 plat: rk3588: sleep: save/restore busscru_mode_con
    8a6a56900 plat: rk3588: fix PD_RPR_RGA31 define error
    f8c0ecd13 plat: rockchip: rk3588: Add a delay before reset mem pd
    b6e301f48 plat: rk3568: move RKPM_SLP_XXX define to pmu.h
    244acd212 plat: px30-s: suspend: add ddr phy reg save
    680b18825 plat: px30-s: refactor ddr dfs set rate code
    2d7dc684b plat: px30-s: add ddr eye scan func
    f4b4c237c plat: px30-s: workaround x16 bw read training err
    8abe5853e plat: px30-s: add default fsp config
    2fa68b510 plat: px30-s: add de-skew info get from expanded param
    faca0fa70 plat: px30-s: add get_wrlvl_val() fun after f1
    6896d8e94 plat: px30-s: calculate tDQS2DQ before set rate
    2c669790f plat: rockchip: rk3588: scmi: Add support to disable cpu pll
    07caf6d56 plat: rk3588: support pmu_mcu_cec wakeup
    df48286b2 plat: rk3588: sleep: print irq enable status
    400bc8be4 plat: rk3588: fix pmu_power_domain_st function
    f247e00b4 plat: rk3588: modify pmu_mcu secure configuration
    8a89a0515 plat: rk3588: use gpio_int to check external 32k valid
    daeea5137 plat: rockchip: rk3588: scmi: Change npu 300MHz to pvtpll

Change-Id: I1c84c60469372013247a00005464a69e49177270
Signed-off-by: Liang Chen <cl@rock-chips.com>
This commit is contained in:
Liang Chen
2022-07-07 11:32:23 +08:00
parent 35c3e2e438
commit 87885c4874
2 changed files with 1 additions and 1 deletions
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2
RKTRUST/RK3568TRUST.ini
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@@ -5,7 +5,7 @@ MINOR=0
SEC=0
[BL31_OPTION]
SEC=1
PATH=bin/rk35/rk3568_bl31_v1.33.elf
PATH=bin/rk35/rk3568_bl31_v1.34.elf
ADDR=0x00040000
[BL32_OPTION]
SEC=1

BIN
bin/rk35/rk3568_bl31_v1.33.elf → bin/rk35/rk3568_bl31_v1.34.elf
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