tool: ddrbin_tool: update to v1.09 20211130

updata: add support rk3588

Signed-off-by: Zhihuan He <huan.he@rock-chips.com>
Change-Id: I025871d99b45ebacbc891f99d1594f99cbbc9d0b

tools/ddrbin_param.txt

@@ -7,6 +7,7 @@ lp3_freq=
 ddr4_freq=
 lp4_freq=
 lp4x_freq=
+lp5_freq=
 
 uart id=
 uart iomux=
@@ -20,6 +21,7 @@ channel mask=
 stride type=
 standby_idle=
 
+dis_cbt_for_lp4_lp4x=
 dis_printf_training=
 
 ssmod_downspread=
@@ -253,4 +255,57 @@ phy_lp4x_dq_vref_when_odtoff=
 lp4x_dq_vref_when_odtoff=
 lp4x_ca_vref_when_odtoff=
 
+lp5_f1_freq_mhz=
+lp5_f2_freq_mhz=
+lp5_f3_freq_mhz=
+lp5_f4_freq_mhz=
+lp5_f5_freq_mhz=
+phy_lp5_dq_drv_when_odten_ohm=
+phy_lp5_ca_drv_when_odten_ohm=
+phy_lp5_clk_drv_when_odten_ohm=
+lp5_dq_drv_when_odten_ohm=
+phy_lp5_dq_drv_when_odtoff_ohm=
+phy_lp5_ca_drv_when_odtoff_ohm=
+phy_lp5_clk_drv_when_odtoff_ohm=
+lp5_dq_drv_when_odtoff_ohm=
+phy_lp5_odt_ohm=
+lp5_odt_ohm=
+lp5_ca_odt_ohm=
+lp5_drv_pu_cal_odten=
+lp5_drv_pu_cal_odtoff=
+phy_lp5_drv_pull_dn_en_odten=
+phy_lp5_drv_pull_dn_en_odtoff=
+phy_lp5_odten_freq_mhz=
+lp5_dq_odten_freq_mhz=
+phy_lp5_dq_sr_when_odten=
+phy_lp5_ca_sr_when_odten=
+phy_lp5_clk_sr_when_odten=
+phy_lp5_dq_sr_when_odtoff=
+phy_lp5_ca_sr_when_odtoff=
+phy_lp5_clk_sr_when_odtoff=
+lp5_ca_odten_freq_mhz=
+lp5_wck_odt_en_freq=
+lp5_wck_odt=
+phy_lp5_cs_drv_odten=
+phy_lp5_cs_drv_odtoff=
+lp5_odte_ck=
+lp5_odte_cs_en=
+lp5_odtd_ca_en=
+lp5_nt_odt=
+phy_lp5_dq_vref_when_odten=
+lp5_dq_vref_when_odten=
+lp5_ca_vref_when_odten=
+phy_lp5_dq_vref_when_odtoff=
+lp5_dq_vref_when_odtoff=
+lp5_ca_vref_when_odtoff=
+
+ch_mask0=
+ch_mask1=
+bank_mask0=
+bank_mask1=
+bank_mask2=
+bank_mask3=
+rank_mask0=
+rank_mask1=
+
 end

tools/ddrbin_tool_user_guide.txt

@@ -43,6 +43,8 @@ The detail information as following:
 	+---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+
 	| RK3566/RK3568 |   V1.00   |   V1.00  | V1.06 |  V1.00 | V1.00 |        V1.06      |          V1.07          |    X    |
 	+---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+
+	|    RK3588     |   V1.00   |   V1.00  |   X   |  V1.00 | V1.00 |        V1.00      |            X            |    X    |
+	+---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+
 
 * UART info
 
@@ -61,7 +63,7 @@ dis_cbt_for_lp4_lp4x: 1: will disbaled CBT for lp4/lp4x; 0: will enable CBT for
 
 * DDR (final) freq
 
-For RV1126/RV1109, RK3566/RK3568, the frequencies as follows can choose to final freq in loader.
+For RV1126/RV1109, RK3566/RK3568, RK3588, the frequencies as follows can choose to final freq in loader.
 
 ddr2_freq: ddr2 frequency,  unit:MHz.
 lp2_freq: lpddr2 frequency,  unit:MHz.
@@ -70,6 +72,7 @@ lp3_freq: lpddr3 frequency,  unit:MHz.
 ddr4_freq: ddr4 frequency,  unit:MHz.
 lp4_freq: lpddr4 frequency,  unit:MHz.
 lp4x_freq: lpddr4x frequency,  unit:MHz.
+lp5_freq: lpddr5 frequency,  unit:MHz.
 
 The 'X' as follows means not support change frequencies by tool.
 +---------------+-----------------------------------------------------------------+
@@ -104,6 +107,8 @@ The 'X' as follows means not support change frequencies by tool.
 |    RK3568     |        DDR3/LP3: 324,396,528,630,780,920,1056,1184              |
 |               |   DDR4/LP4/LP4X: 324,396,528,630,780,920,1056,1184,1332,1560    |
 +---------------+-----------------------------------------------------------------+
+|    RK3588     |     LP4/LP4x [306.5MHz - 2133MHz]; LP5: [400MHz - 2750MHz]      |
++---------------+-----------------------------------------------------------------+
 
 * DDR frequencies(add more)
 
@@ -114,7 +119,8 @@ ddr2_f4_freq_mhz: ddr2 frequency number 4,  unit:MHz.
 ddr2_f5_freq_mhz: ddr2 frequency number 5,  unit:MHz.
 ...
 
-ddr*_f*_freq_mhz/lp*_f*_freq_mhz: Only RV1126/RV1109, RK3566/RK3568 used.The program will initialize dram by following order.
+ddr*_f*_freq_mhz/lp*_f*_freq_mhz: ddr*_f*_freq_mhz/lp*_f*_freq_mhz: Only RV1126/RV1109, RK3566/RK3568, RK3588 used.
+The program will initialize dram by following order.
 for example: ddr4_f1_freq_mhz --> ddr4_f2_freq_mhz --> ddr4_f3_freq_mhz --> ddr4_freq.
 And the final frequency is 'ddr4_freq' to boot system.
 So it is better to arrange the frequency values in order as above. That means the max freq is in final freq(lp*/ddr*_freq) and the min freq is in 'ddr*/lp*_f1_freq_mhz'.
@@ -243,3 +249,6 @@ lp4*_ca_vref_when_odten: The DRAM VrefCA when DRAM CA odt on. uint: parts per th
 phy_lp4_dq_vref_when_odtoff:  The PHY VrefDQ when PHY odt off. uint: parts per thousand.
 lp4_dq_vref_when_odtoff: The DRAM VrefDQ when DRAM DQ/DQS odt off. uint: parts per thousand.
 lp4_ca_vref_when_odtoff: The DRAM VrefCA when DRAM CA odt off. uint: parts per thousand.
+
+* hash info
+ch/bank/rank_mask*: is used to DDR address hash mask.