px30: bl31: update version to v1.27

Build from ATF commit:
	96550638e plat: px30-s: dram: phy io ctrl save and resume
Update feature:
	96550638e plat: px30-s: dram: phy io ctrl save and resume
	61fb26d65 plat: px30-s: dram: fix ck/ckb to low before deepsleep
	90c6c51f7 plat: rockchip: rk3588: Set gpll source clock div to 0
	c5157a42e plat: px30-s: Restore DDR PHY dfi low power function
	0de2c3db8 plat: px30: sleep: enter ddr sref by software
	16fda9dd6 plat: px30s: suspend: add ddr resume support
	91188bd6f plat: px30: suspend: support ddr resume

Signed-off-by: Zhihuan He <huan.he@rock-chips.com>
Change-Id: I42b2ac01c74ad3f17a7e300fcb214993c82fe057
This commit is contained in:
Zhihuan He
2022-02-17 17:39:19 +08:00
committed by Jianhong Chen
parent f74d206a48
commit 9940cf2a75
2 changed files with 1 additions and 1 deletions

View File

@@ -5,7 +5,7 @@ MINOR=0
SEC=0
[BL31_OPTION]
SEC=1
PATH=bin/rk33/px30_bl31_v1.26.elf
PATH=bin/rk33/px30_bl31_v1.27.elf
ADDR=0x00040000
[BL32_OPTION]
SEC=1