rk3566: ddr: update ddrbin to v1.20
build from: 77170a5e90 rk356x: ddr: en lp4/4x rx odt when freq greater than 600MHz build command: ./make.sh rk3568 update feature: 1. Update DDR3/LPDDR3 rd/wr training pattern to improve read and write signal margin. 2. Fixed 6GB LPDDR3/4 initialization failure problem. 3. LPDDR4/4X enable 780MHz read odt。 4. Eanble read/write vref training to improve compatibility.(can be disable using ddrbin_tool). Signed-off-by: Tang Yun ping <typ@rock-chips.com> Change-Id: I0fe632a8959361517c3dee6678addae87dfc8ad7
This commit is contained in:
committed by
Jianhong Chen
parent
f48deced82
commit
d87e6485d6
@@ -5,7 +5,7 @@ MAJOR=1
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MINOR=1
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[CODE471_OPTION]
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NUM=1
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Path1=bin/rk35/rk3566_ddr_1056MHz_v1.18.bin
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Path1=bin/rk35/rk3566_ddr_1056MHz_v1.20.bin
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Sleep=1
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[CODE472_OPTION]
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NUM=1
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@@ -14,10 +14,10 @@ Path1=bin/rk35/rk356x_usbplug_v1.17.bin
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NUM=2
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LOADER1=FlashData
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LOADER2=FlashBoot
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FlashData=bin/rk35/rk3566_ddr_1056MHz_v1.18.bin
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FlashData=bin/rk35/rk3566_ddr_1056MHz_v1.20.bin
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FlashBoot=bin/rk35/rk356x_spl_v1.13.bin
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[OUTPUT]
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PATH=rk356x_spl_loader_v1.18.113.bin
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PATH=rk356x_spl_loader_v1.20.113.bin
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[SYSTEM]
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NEWIDB=true
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[FLAG]
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@@ -5,7 +5,7 @@ MAJOR=1
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MINOR=8
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[CODE471_OPTION]
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NUM=1
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Path1=bin/rk35/rk3566_ddr_1056MHz_v1.18.bin
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Path1=bin/rk35/rk3566_ddr_1056MHz_v1.20.bin
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Sleep=1
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[CODE472_OPTION]
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NUM=1
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@@ -14,10 +14,10 @@ Path1=bin/rk35/rk356x_usbplug_nand_v1.04.bin
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NUM=2
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LOADER1=FlashData
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LOADER2=FlashBoot
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FlashData=bin/rk35/rk3566_ddr_1056MHz_v1.18.bin
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FlashData=bin/rk35/rk3566_ddr_1056MHz_v1.20.bin
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FlashBoot=bin/rk35/rk356x_spl_nand_v1.14.bin
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[OUTPUT]
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PATH=rk3566_spl_loader_nand_v1.18.107.bin
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PATH=rk3566_spl_loader_nand_v1.20.107.bin
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[SYSTEM]
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NEWIDB=true
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[FLAG]
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Binary file not shown.
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BIN
bin/rk35/rk3566_ddr_1056MHz_v1.20.bin
Normal file
BIN
bin/rk35/rk3566_ddr_1056MHz_v1.20.bin
Normal file
Binary file not shown.
Binary file not shown.
Binary file not shown.
BIN
bin/rk35/rk3566_ddr_920MHz_v1.20.bin
Normal file
BIN
bin/rk35/rk3566_ddr_920MHz_v1.20.bin
Normal file
Binary file not shown.
@@ -1,5 +1,26 @@
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# RK3566 Release Note
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## rk3566_ddr_{1056...920}MHz_v1.20.bin
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| 时间 | 文件 | 编译 commit | 重要程度 |
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| ---------- | :--------------------------------- | ----------- | -------- |
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| 2024-01-12 | rk3566_ddr_{1056...920}MHz_v1.20.bin | 77170a5e90 | 重要 |
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### New
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1. 可通过工具配置tRFC值。
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2. 增加read/write vref training,提高读写稳定性。
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### Fixed
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| Index | 重要程度 | 更新说明 | 问题现象 | 问题来源 |
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| ----- | -------- | -------------------------------------------------------- | ------------------------------------- | -------- |
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| 1 | 重要 | 更新DDR3/LPDDR3 rd/wr training码型提高读写信号余量 | 优化DDR3/LPDDR3读写信号余量 | - |
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| 2 | 重要 | 修正6GB LPDDR3/4初始化失败问题 | 6GB LPDDR3/4 初始化时卡住 | - |
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| 3 | 重要 | LPDDR4/4X 780Mhz开启read odt,改善部分颗粒780MHz下稳定性 | 部分LPDDR4/4X颗粒780M下read稳定性较差 | - |
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------
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## rk3568_bl31_ultra_v2.16.elf
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| 时间 | 文件 | 编译 commit | 重要程度 |
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@@ -1,5 +1,26 @@
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# RK3566 Release Note
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## rk3566_ddr_{1056...920}MHz_v1.20.bin
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| Date | File | Build commit | Severity |
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| ---------- | ------------------------------------ | ------------ | --------- |
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| 2024-01-12 | rk3566_ddr_{1056...920}MHz_v1.20.bin | 77170a5e90 | important |
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### New
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1. The tRFC value can be configured through ddrbin_tools.
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1. Add read write vref trining to improve compatibility.
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### Fixed
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| Index | Severity | Update | Issue description | Issue source |
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| ----- | --------- | ------------------------------------------------------------ | ---------------------------------------------------- | ------------ |
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| 1 | important | Update DDR3/LPDDR3 rd/wr training pattern to improve read and write signal margin | Optimize DDR3/LPDDR3 read and write signal margin | - |
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| 2 | important | Fixed 6GB LPDDR3/4 initialization failure problem | 6GB LPDDR3/4 panic during DDR initialization | - |
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| 3 | important | Enable LPDDR4/4X read odt under780M to implove stability. | Some LPDDR4/4X particles have poor stability at 780M | - |
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------
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## rk3568_bl31_ultra_v2.16.elf
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| Date | File | Build commit | Severity |
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