rk3566: ddr: update ddrbin to v1.20

build from:
	77170a5e90 rk356x: ddr: en lp4/4x rx odt when freq greater than 600MHz

build command:
	./make.sh rk3568

update feature:
	1. Update DDR3/LPDDR3 rd/wr training pattern to improve
read and write signal margin.
	2. Fixed 6GB LPDDR3/4 initialization failure problem.
	3. LPDDR4/4X enable 780MHz read odt。
	4. Eanble read/write vref training to improve
compatibility.(can be disable using ddrbin_tool).

Signed-off-by: Tang Yun ping <typ@rock-chips.com>
Change-Id: I0fe632a8959361517c3dee6678addae87dfc8ad7
This commit is contained in:
Tang Yun ping
2024-01-12 15:16:16 +08:00
committed by Jianhong Chen
parent f48deced82
commit d87e6485d6
10 changed files with 48 additions and 6 deletions

View File

@@ -5,7 +5,7 @@ MAJOR=1
MINOR=1
[CODE471_OPTION]
NUM=1
Path1=bin/rk35/rk3566_ddr_1056MHz_v1.18.bin
Path1=bin/rk35/rk3566_ddr_1056MHz_v1.20.bin
Sleep=1
[CODE472_OPTION]
NUM=1
@@ -14,10 +14,10 @@ Path1=bin/rk35/rk356x_usbplug_v1.17.bin
NUM=2
LOADER1=FlashData
LOADER2=FlashBoot
FlashData=bin/rk35/rk3566_ddr_1056MHz_v1.18.bin
FlashData=bin/rk35/rk3566_ddr_1056MHz_v1.20.bin
FlashBoot=bin/rk35/rk356x_spl_v1.13.bin
[OUTPUT]
PATH=rk356x_spl_loader_v1.18.113.bin
PATH=rk356x_spl_loader_v1.20.113.bin
[SYSTEM]
NEWIDB=true
[FLAG]

View File

@@ -5,7 +5,7 @@ MAJOR=1
MINOR=8
[CODE471_OPTION]
NUM=1
Path1=bin/rk35/rk3566_ddr_1056MHz_v1.18.bin
Path1=bin/rk35/rk3566_ddr_1056MHz_v1.20.bin
Sleep=1
[CODE472_OPTION]
NUM=1
@@ -14,10 +14,10 @@ Path1=bin/rk35/rk356x_usbplug_nand_v1.04.bin
NUM=2
LOADER1=FlashData
LOADER2=FlashBoot
FlashData=bin/rk35/rk3566_ddr_1056MHz_v1.18.bin
FlashData=bin/rk35/rk3566_ddr_1056MHz_v1.20.bin
FlashBoot=bin/rk35/rk356x_spl_nand_v1.14.bin
[OUTPUT]
PATH=rk3566_spl_loader_nand_v1.18.107.bin
PATH=rk3566_spl_loader_nand_v1.20.107.bin
[SYSTEM]
NEWIDB=true
[FLAG]

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@@ -1,5 +1,26 @@
# RK3566 Release Note
## rk3566_ddr_{1056...920}MHz_v1.20.bin
| 时间 | 文件 | 编译 commit | 重要程度 |
| ---------- | :--------------------------------- | ----------- | -------- |
| 2024-01-12 | rk3566_ddr_{1056...920}MHz_v1.20.bin | 77170a5e90 | 重要 |
### New
1. 可通过工具配置tRFC值。
2. 增加read/write vref training提高读写稳定性。
### Fixed
| Index | 重要程度 | 更新说明 | 问题现象 | 问题来源 |
| ----- | -------- | -------------------------------------------------------- | ------------------------------------- | -------- |
| 1 | 重要 | 更新DDR3/LPDDR3 rd/wr training码型提高读写信号余量 | 优化DDR3/LPDDR3读写信号余量 | - |
| 2 | 重要 | 修正6GB LPDDR3/4初始化失败问题 | 6GB LPDDR3/4 初始化时卡住 | - |
| 3 | 重要 | LPDDR4/4X 780Mhz开启read odt改善部分颗粒780MHz下稳定性 | 部分LPDDR4/4X颗粒780M下read稳定性较差 | - |
------
## rk3568_bl31_ultra_v2.16.elf
| 时间 | 文件 | 编译 commit | 重要程度 |

View File

@@ -1,5 +1,26 @@
# RK3566 Release Note
## rk3566_ddr_{1056...920}MHz_v1.20.bin
| Date | File | Build commit | Severity |
| ---------- | ------------------------------------ | ------------ | --------- |
| 2024-01-12 | rk3566_ddr_{1056...920}MHz_v1.20.bin | 77170a5e90 | important |
### New
1. The tRFC value can be configured through ddrbin_tools.
1. Add read write vref trining to improve compatibility.
### Fixed
| Index | Severity | Update | Issue description | Issue source |
| ----- | --------- | ------------------------------------------------------------ | ---------------------------------------------------- | ------------ |
| 1 | important | Update DDR3/LPDDR3 rd/wr training pattern to improve read and write signal margin | Optimize DDR3/LPDDR3 read and write signal margin | - |
| 2 | important | Fixed 6GB LPDDR3/4 initialization failure problem | 6GB LPDDR3/4 panic during DDR initialization | - |
| 3 | important | Enable LPDDR4/4X read odt under780M to implove stability. | Some LPDDR4/4X particles have poor stability at 780M | - |
------
## rk3568_bl31_ultra_v2.16.elf
| Date | File | Build commit | Severity |