Mirrors/rkbin
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

rk3568: bl31 ultra: update version to v2.05

Browse Source 
Build from ATF commit:
    7bc959925 plat: rk3568: dmc: update version to V1.01 and add ddr_get_freq_info
update feature:
    7bc959925 plat: rk3568: dmc: update version to V1.01 and add ddr_get_freq_info
    d2e0ef53d plat: rk3568: select the default suspend 32k clock from the PVTM
    f8297ce88 rockchip_exceptions: adjust the usage of uartdbg_uart_info.tgt_cpu
    d053a1087 rockchip: fiq debugger: don't disable fiq if fiq from el2
    354236216 rockchip_exceptions: save/restore el2 register if fiq-debugger from el2
    02bab0c8f BACKPORT: lib: el3_runtime: Fix SPE system registers in el2_sysregs_context
    2c7c36d92 plat: rk3568: support cache ecc.
    cda1658bc plat: rk3568: config the pmugrf_reset_hold bit
    c2d509965 plat: rk3568: save and restore PMUCRU_PMUCLKSEL_CON00
    9b05de3a1 plat: rk3568: dump the wakeup irq
    270aa3847 plat: rk3568: dmc: rectiyf LPDDR4 MR14 value

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I3e00968594fae0ceed781dbc130157b6d114cf76
This commit is contained in:
Joseph Chen
2021-06-08 17:24:32 +08:00
parent 7be392f70c
commit feb5aa082b
2 changed files with 1 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
RKTRUST/RK3566TRUST_ULTRA.ini
View File

@@ -5,7 +5,7 @@ MINOR=0
SEC=0
[BL31_OPTION]
SEC=1
PATH=bin/rk35/rk3568_bl31_ultra_v2.04.elf
PATH=bin/rk35/rk3568_bl31_ultra_v2.05.elf
ADDR=0x00040000
[BL32_OPTION]
SEC=1

BIN
bin/rk35/rk3568_bl31_ultra_v2.04.elf → bin/rk35/rk3568_bl31_ultra_v2.05.elf
View File

Binary file not shown.