build from rockit-ko commit in master branch:
c9653fe9 hpmcu: update version to v1.5.3
build from hal commit in master branch:
a76806e7 project: common: riscv: change riscv toolchain to xpack
Signed-off-by: Chuanhu Sun <aaron.sun@rock-chips.com>
Change-Id: I3e3d75ac1bfc0cfb14d239ea74ce7a1fdb154ba2
build in:
e5b9702 rk3326/px30: ddr: Update ddr bin to V2.08 20220817
update feature:
80092f9 rk3326/rk3326-s: reserved for maskrom to add special
parameters
Signed-off-by: Zhihuan He <huan.he@rock-chips.com>
Change-Id: I55d692a5863eb7aa0640cd5a3ea40ba4b2f6c1eb
build in:
e5b9702 rk3326/px30: ddr: Update ddr bin to V2.08 20220817
update feature:
80092f9 rk3326/rk3326-s: reserved for maskrom to add special
parameters
Signed-off-by: Zhihuan He <huan.he@rock-chips.com>
Change-Id: Ib7a7fb27728c4c2a862d836496a1e7836faa58b9
Build from:
ec2fae0c96 rk356x: ddr: update ddr bin to v1.15
Update feature:
25f78a9a5d drivers: ram: rv1106: Initial version v1.10 20221108
1. Set reg_fb1xclk_invdelaysel_dqcmd to 0x15 except DDR2
2. Simplify print
3. Set DPLL Fvco_max of BGA to 3800MHz
4. Config sw_done to change INIT7 in set_ds_odt()
5. Use bitflip pattern to do write tain
6. Keep CLK skew = 0x80, and adjust DQS Tx skew according to wrlvl
7. Update DDR4 dram vref by A7 of MR6
8. Fix value of SCHED
9. Fix value of RANKCTL
Signed-off-by: Wesley Yao <wesley.yao@rock-chips.com>
Change-Id: I6d4a71228636c7ff56d336ca138b071706363ed8
build from:
ec2fae0c96 rk356x: ddr: update ddr bin to v1.15
update feature:
4023ab4e29 rk3568: ddr: use upctl control dfi_init_start/complete
f254ec2b5d rk356x: Add adjust the hold timing of the digital to
analog interface
a14b1383ca drivers: rk356x: Add automatic temperature derating
for LPDDR4(X)
Signed-off-by: Zhihuan He <huan.he@rock-chips.com>
Change-Id: Ic0285f391c167654a433cb81a556382f2ce943eb
build from:
ec2fae0c96 rk356x: ddr: update ddr bin to v1.15
update feature:
4023ab4e29 rk3568: ddr: use upctl control dfi_init_start/complete
f254ec2b5d rk356x: Add adjust the hold timing of the digital to
analog interface
a14b1383ca drivers: rk356x: Add automatic temperature derating
for LPDDR4(X)
Signed-off-by: Zhihuan He <huan.he@rock-chips.com>
Change-Id: I732fe0346555a002a3bdd6b987260a2fb3dbab1f
from commit:
eaaeb1: rk356x: mmc: add ffu for FEMDNN064G_A3A44
update feature:
Support new spiflash
Change-Id: Ie3cc0509c8fdc802e994fc7166a092a90b1c0794
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
build from commit:
rtt:05d3e965d#hal:b569247c#battery_ipc:bc3785d
build from rt-thread commit in develop branch:
05d3e965d:[BSP] rk2108: board: support rk2108d_evb_v20
build from hal commit in master branch:
b569247c:lib: hal: cru: rk3588: Fix select rate from osc24m
build from battery-ipc commit in master branch:
bc3785d:add color_mode control logic
Signed-off-by: chujin.zhou <chujin.zhou@rock-chips.com>
Change-Id: Ieea9fb5b6bf13fa1b6034dce024741810d91ff24
build from commit:
rtt:2ede82a43#hal:b569247c#battery_ipc:efaec692c
rtt cherry-pick 8b1555259: add gc2093 driver
build from rt-thread commit in develop branch:
2ede82a43:[BSP]: rockchip: rv1106-mcu: define various boards
build from hal commit in master branch:
b569247c:lib: hal: cru: rk3588: Fix select rate from osc24m
build from battery-ipc commit in master branch:
efaec692c:fast_ae: fixes illegal access to 0x0
Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com>
Change-Id: I62675761ec09ae21763d92e68c6354cd5db270ba
Build from:
8fef64cfb9 dram_init: rv1126: Update to v1.09
Update feature:
0d2a0f8f86 drivers: ram: rv1126: Detect bus width of DDR3 through read gate, and init DDR3 again
181bc4650d drivers: ram: rv1126: Fix read_mr()
1911c18330 drivers: ram: rv1126: Fix calc of LPDDR4(X) wrlvl_result min_val
9ebc05219a drivers: ram: rv1126: Fix compiler error if CONFIG_ROCKCHIP_TPL_INIT_DRAM_TYPE == 8
56f3e68665 rv1126: ddr: Fix set of t_xs_x32, t_xs_abort_x32 and t_xs_fast_x32
1c7093e71f drivers: ram: rv1126: define CONFIG_CMD_DDR_TEST_TOOL by default when CONFIG_DRAM_INIT_BUILD
d393fbb5da drivers: ram: rv1126: Adjust the time of sdram_detect_dbw of LPDDR3
Signed-off-by: Wesley Yao <wesley.yao@rock-chips.com>
Change-Id: I93ed60c3967a1f5c2c8e11d35d901d61e29148cc
Build from ATF commit:
6f45bba91 plat: px30: do second reset if rbrom in px30s
update feature:
6f45bba91 plat: px30: do second reset if rbrom in px30s
99f86f801 plat: px30: disable reset out if reboot normal
8932810e4 plat: px30: resolve misjudgments about reboot_flag
ad0d2e72c plat: px30: compatible with the old loader
01ab909ae rockchip: support plat_bl31_inner.ld.S
Change-Id: Iaa339cb0b89c642a36f21b096a0f789d1a172221
Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
Build from ATF commit:
6f45bba91 plat: px30: do second reset if rbrom in px30s
update feature:
6f45bba91 plat: px30: do second reset if rbrom in px30s
99f86f801 plat: px30: disable reset out if reboot normal
8932810e4 plat: px30: resolve misjudgments about reboot_flag
ad0d2e72c plat: px30: compatible with the old loader
01ab909ae rockchip: support plat_bl31_inner.ld.S
Change-Id: I7a9711e7bbc20775ee9d0653ad0c5d054f6d1d11
Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
Build from ATF commit:
6f45bba91 plat: px30: do second reset if rbrom in px30s
update feature:
6f45bba91 plat: px30: do second reset if rbrom in px30s
99f86f801 plat: px30: disable reset out if reboot normal
8932810e4 plat: px30: resolve misjudgments about reboot_flag
ad0d2e72c plat: px30: compatible with the old loader
01ab909ae rockchip: support plat_bl31_inner.ld.S
Change-Id: I7425fb7d230f1cb8c4a767f8cacf0e0fe6b61b25
Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
Build from ATF commit:
cddd6f52e plat: rk3568: save/restore all GICR in suspend
update feature:
cddd6f52e plat: rk3568: save/restore all GICR in suspend
a410f9c46 plat: rockchip: rk3528: Add scmi clock
a953ce24b plat: rk3588: dmc: disable derate instead of derate_mr4_pause_fc
6f45bba91 plat: px30: do second reset if rbrom in px30s
99f86f801 plat: px30: disable reset out if reboot normal
8932810e4 plat: px30: resolve misjudgments about reboot_flag
90a45ece3 rockchip: support rk3528
Signed-off-by: shengfei Xu <xsf@rock-chips.com>
Change-Id: Ic8af9dfcf843cba5a11708633a78fb4a16f26a4d
build from commit:
rtt:2ede82a43#hal:b569247c#battery_ipc:efaec692c
build from rt-thread commit in develop branch:
2ede82a43:[BSP]: rockchip: rv1106-mcu: define various boards
build from hal commit in master branch:
b569247c:lib: hal: cru: rk3588: Fix select rate from osc24m
build from battery-ipc commit in master branch:
efaec692c:fast_ae: fixes illegal access to 0x0
Signed-off-by: chujin.zhou <chujin.zhou@rock-chips.com>
Change-Id: If41fbee0e538e197a740dc598bb3401efec2c1a7
build from:
1089bf090 plat: rk3288: Set pmu can be reset by 1st global reset
update feature:
1089bf090 plat: rk3288: Set pmu can be reset by 1st global reset
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I82b13377a3b252a26e044a7b50f6acd409e999ca
Build from ATF commit:
0252d5c8f plat: rk3308: disable pclk_wdt while system suspend
update feature:
0252d5c8f plat: rk3308: disable pclk_wdt while system suspend
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I7c4b5a71424459d845c3b51098b4259bc396a4cc
build from rockit-ko commit in master branch:
576377cb mcu: update mcu bin to v1.50
build from hal commit in master branch:
a76806e7 project: common: riscv: change riscv toolchain to xpack
Signed-off-by: Chuanhu Sun <aaron.sun@rock-chips.com>
Change-Id: I03a9d64be28267bb1e13361fdc528732ba2bc7b8
Build from ATF commit:
686b5c48b plat: rk3588: sleep: disable gpio 1/3 int if mcu_wakup
update feature:
686b5c48b plat: rk3588: sleep: disable gpio 1/3 int if mcu_wakup
af5ab70fc plat: rockchip: set "plat_uart_base=0" if uart disable
3eb5ebec2 plat: rockchip: uart: wait no busy before restore
6d4252c24 plat: rk3588: secure: only support ddr-4ch,stride-en by default
dc491ee36 plat: rk3588: secure: support config for different ddr-channel number
304673533 plat: rk3588: sleep: support different ddr-channel number
0f4f44e43 plat: rk3588: ddr: add some ddr-channel related functions
9dbfb40af plat: rk3588: secure: simplify secure_region_init function
a7e0c6c06 plat: rk3588: secure: config dsu_mp_sec can access all ddr-regions
988ba1e81 plat: rk3588: move secure related code to secure.c
dee611ca6 plat: rockchip: rk3588: dmc: get LPDDR5 mr16 value from fsp_param
73824e139 plat: rockchip: rk3588: dmc: add support M0_PARAM_INT_VOP
f175a33cf plat: rockchip: rk3588: dmc: force reset if the ddr_m0 is on the halt
a9e5261be plat: rockchip: rk3588: dmc: add bits mask for low power config
8b4543970 plat: rk3588: enable ERRATA_A55_1530923
Change-Id: I041acae523c3b2dba7eb1677411f32d4f1aadba5
Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
from commit:
65048d1 platform: rk3568: Update to v1.15
update feature:
Support new spiflash
Change-Id: I4fbcdb5c5b619f47c5600f2b2332fcbcdbb79d78
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
from commit:
482e146 src: spinand: Support udpate IDB in Firmware.img
update feature:
Support udpate IDB in Firmware.img
Change-Id: I66ea110bab639775422f77b77b0467b62e1e4fe9
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Build from OPTEE commit in develop-next branch:
4542e1efd rk3588: secure-region: support config for different ddr-channel number
Update features:
4542e1efd rk3588: secure-region: support config for different ddr-channel numbe
Change-Id: I8ea1bd457de2581469001b3d7edf7a1e56ab9014
Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
Build from OPTEE commit in develop-next branch:
d84087907 plat-rockchip: main: not call rk_uart_init if rk_atags disable serial
Update features:
d84087907 plat-rockchip: main: not call rk_uart_init if rk_atags disable serial
cf59606f0 rk3308: delete key reader code which is unused
0af3483b2 pta: crypto_service: support user ta call hard cipher
778974be4 core: tee: calculate node hash with meta default
4167319d3 core: tee: recreate dirf.db if open dirf.db fail
Signed-off-by: Hisping Lin <hisping.lin@rock-chips.com>
Change-Id: I9820efbb5f85239df8ff490710c3e7d3269e976f
Build from OPTEE commit in develop-next branch:
d84087907 plat-rockchip: main: not call rk_uart_init if rk_atags disable serial
Update features:
d84087907 plat-rockchip: main: not call rk_uart_init if rk_atags disable serial
f22bb78ed rk3358: set user dctrl before key reader init
Signed-off-by: Hisping Lin <hisping.lin@rock-chips.com>
Change-Id: Icd3290d45c697048a3debcd495666391835651ad
Build from OPTEE commit in develop-next branch:
d84087907 plat-rockchip: main: not call rk_uart_init if rk_atags disable serial
Update features:
d84087907 plat-rockchip: main: not call rk_uart_init if rk_atags disable serial
3e2bbe510 rk3326: set user dctrl before key reader init
Signed-off-by: Hisping Lin <hisping.lin@rock-chips.com>
Change-Id: I521b9954fa190355bb0e1fc192696eb69ada6095
Build from OPTEE commit in develop-next branch:
d84087907 plat-rockchip: main: not call rk_uart_init if rk_atags disable serial
Update features:
d84087907 plat-rockchip: main: not call rk_uart_init if rk_atags disable serial
3e2bbe510 rk3326: set user dctrl before key reader init
Signed-off-by: Hisping Lin <hisping.lin@rock-chips.com>
Change-Id: I065f9842ad3cf836f04200ee05f825d3d39a6a8b
Build from OPTEE commit in develop-next branch:
d84087907 plat-rockchip: main: not call rk_uart_init if rk_atags disable serial
Update features:
d84087907 plat-rockchip: main: not call rk_uart_init if rk_atags disable serial
7448ce1a1 rk3568: modify key reader init function
ad04716e7 rk3568: do not need check ecc when sbpi read without ecc
87d94c5ef plat-rockchip: main: support hdcp key init via tee_entry_fast
0af3483b2 pta: crypto_service: support user ta call hard cipher
778974be4 core: tee: calculate node hash with meta default
4167319d3 core: tee: recreate dirf.db if open dirf.db fail
Signed-off-by: Hisping Lin <hisping.lin@rock-chips.com>
Change-Id: I12388d64e19600b8c0c51c24b990e4af7d297d84
Build from OPTEE commit in develop-next branch:
d84087907 plat-rockchip: main: not call rk_uart_init if rk_atags disable serial
Update features:
d84087907 plat-rockchip: main: not call rk_uart_init if rk_atags disable serial
87d94c5ef plat-rockchip: main: support hdcp key init via tee_entry_fast
0af3483b2 pta: crypto_service: support user ta call hard cipher
778974be4 core: tee: calculate node hash with meta default
4167319d3 core: tee: recreate dirf.db if open dirf.db fail
Signed-off-by: Hisping Lin <hisping.lin@rock-chips.com>
Change-Id: I692f94d44fd15642b3c052c5574588c2c8ad22a2
Build from OPTEE commit in develop-next branch:
d84087907 plat-rockchip: main: not call rk_uart_init if rk_atags disable serial
Update features:
d84087907 plat-rockchip: main: not call rk_uart_init if rk_atags disable serial
778974be4 core: tee: calculate node hash with meta default
4167319d3 core: tee: recreate dirf.db if open dirf.db fail
7a0581630 scripts: commit_bin: support more platforms
f5add58be core: TEE_GenerateKey support RSA key e = 3
af506d32e ta verify: close default key for sign ta
78d37d71a core: rpmb: compatible with old RPMB keys
88dd1c910 rk1808: enlarge MAX_XLAT_TABLES to 8
Signed-off-by: Hisping Lin <hisping.lin@rock-chips.com>
Change-Id: I853183ef0acedba4c408088665d95b209d165d33
Build from OPTEE commit in develop-next branch:
d84087907 plat-rockchip: main: not call rk_uart_init if rk_atags disable serial
Update features:
d84087907 plat-rockchip: main: not call rk_uart_init if rk_atags disable serial
778974be4 core: tee: calculate node hash with meta default
4167319d3 core: tee: recreate dirf.db if open dirf.db fail
7a0581630 scripts: commit_bin: support more platforms
f5add58be core: TEE_GenerateKey support RSA key e = 3
af506d32e ta verify: close default key for sign ta
78d37d71a core: rpmb: compatible with old RPMB keys
88dd1c910 rk1808: enlarge MAX_XLAT_TABLES to 8
Signed-off-by: Hisping Lin <hisping.lin@rock-chips.com>
Change-Id: Ic7b79bc66ba6499c141977c551213ae219aa5f00
Build from OPTEE commit in develop-next branch:
d84087907 plat-rockchip: main: not call rk_uart_init if rk_atags disable serial
Update features:
d84087907 plat-rockchip: main: not call rk_uart_init if rk_atags disable serial
87d94c5ef plat-rockchip: main: support hdcp key init via tee_entry_fast
Signed-off-by: Hisping Lin <hisping.lin@rock-chips.com>
Change-Id: I2fbbe81a5b9eacb9981cd117c27ea763fc9ef7c1
build from rockit-ko commit in master branch:
7e8fe8af [mcu]: add wrap end log and delete unsed code
build from hal commit in master branch:
a76806e7 project: common: riscv: change riscv toolchain to xpack
Signed-off-by: Chuanhu Sun <aaron.sun@rock-chips.com>
Change-Id: I2cf39f8144dfb9211db9c658220be3ed18f70fbb
from commit:
55a904 src: spinand: Support MX35UF1GE4AD MX35UF2GE4AD
update feature:
Support MX35UF1GE4AD MX35UF2GE4AD
Change-Id: I30f9edf37fa8f50affc487bc879585308c9e1918
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
from commit:
97d7a6 platform: rk3308: Update to v1.39
update feature:
sftl Check the data in second page
Change-Id: I79acc109d613a2402f2b3aeeb0b5436eea835c15
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
