build from:
5b44f28 dram init: rk1808: update ddr bin version to v1.04
update feature:
1. update cpu and npu's priorty to 1, vop's priority to 3
and ohter master's priority to 2.
2. agingx0 set to 0x4, aging0 set to 0x33, aging1,2 set to 0xff.
Change-Id: I98e789eece9efcd913c450cf773985139fc8d9e1
Signed-off-by: Tang Yun ping <typ@rock-chips.com>
build from:
5b44f28 dram init: rk1808: update ddr bin version to v1.04
update feature:
1. update cpu and npu's priorty to 1, vop's priority to 3
and ohter master's priority to 2.
2. agingx0 set to 0x4, aging0 set to 0x33, aging1,2 set to 0xff.
Change-Id: I0a53ccfeac377cb63fbfeb3f2d7eb7718103ef73
Signed-off-by: Tang Yun ping <typ@rock-chips.com>
Build from ATF commit:
d25b046 plat: rk3368: suspend: no need to save/restore mcu data
update feature:
d25b046 plat: rk3368: suspend: no need to save/restore mcu data
d27bda2 plat: rk3368: change bl31_base to 0x40000
17dda82 plat: rk3368: suspend: disable/restore watchdog
73ddb15 plat: rockchip: common: update LPDDR4 spec timing
868b602 plat: rockchip: common: update dram spec ODT timing
50f2e2e plat: rockchip: fiq_dfs: add isb and dsb after tlbialle3
7018b41 rockchip: add a script to commit elf to rkbin
19ab7df plat: rk1808: set all region as secure to all master
31ff1d0 plat: rockchip: set "plat_uart_base=0" if uart disable
99ca711 plat: rockchip: uart: wait no busy before restore
Change-Id: I6e302985ad907d570ef6743fd52c829c4a31b3a0
Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
build from optee commit in develop-rk3228 branch:
cdfc713f thread: support configurable 2T mode
Change-Id: I482fea276bc79a03fc247989ccb896ca380ddc0a
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
build from optee commit in develop-rk3228 branch:
1d667fcf thread: alloc rpc arg if rpc_arg == null
update feature:
d65a69f4 ddr: rk3288: add ddr_wait_vop_finish() in _ddr_adjust_config()
aa67a2b8 rockchip: flush all cache when cpu off
7a43c16b plat-rockchip: config: remove RK3368 related code
Change-Id: I9675bd69e5a31f9d9ae711e9e32a037c3d707ff9
Signed-off-by: Hisping Lin <hisping.lin@rock-chips.com>
build from optee commit in develop-rk3228 branch:
1d667fcf thread: alloc rpc arg if rpc_arg == null
update feature:
d65a69f4 ddr: rk3288: add ddr_wait_vop_finish() in _ddr_adjust_config()
aa67a2b8 rockchip: flush all cache when cpu off
7a43c16b plat-rockchip: config: remove RK3368 related code
Change-Id: Ib3105decc6e4867b3c4fad5b11f75507fbb0fe79
Signed-off-by: Hisping Lin <hisping.lin@rock-chips.com>
build from optee commit in develop-rk3228 branch:
1d667fcf thread: alloc rpc arg if rpc_arg == null
update feature:
d65a69f4 ddr: rk3288: add ddr_wait_vop_finish() in _ddr_adjust_config()
aa67a2b8 rockchip: flush all cache when cpu off
7a43c16b plat-rockchip: config: remove RK3368 related code
Change-Id: I392bd2f9278c5e505a210b10e6f98d55adb12296
Signed-off-by: Hisping Lin <hisping.lin@rock-chips.com>
build from optee commit in develop-rk3228 branch:
1d667fcf thread: alloc rpc arg if rpc_arg == null
update feature:
d65a69f4 ddr: rk3288: add ddr_wait_vop_finish() in _ddr_adjust_config()
aa67a2b8 rockchip: flush all cache when cpu off
7a43c16b plat-rockchip: config: remove RK3368 related code
Change-Id: I5b758a7e4c9223c9bc9099a2bce2343f0df25169
Signed-off-by: Hisping Lin <hisping.lin@rock-chips.com>
build from optee:
aa67a2b rockchip: flush all cache when cpu off
update feature:
aa67a2b rockchip: flush all cache when cpu off
6c02489 scripts: optimize build scripts
805c30d scripts: add checkbuild.sh to build all platforms
42681ce rockchip: add memtest driver
c69c4c3 core: driver: add rk i2c support
3698c16 rockchip: add memory dump interface
622851f rockchip: add mdelay() function
e7666c9 rockchip: implement switch_to_secondary_cpu()
c3a5b73 core: arm: support boot from secondary cpu
2d906fe script: update build script and pack tools
670938f core: arm32: add cortex-a17 l2ctlr access function
60b0f99 console_init: set serial enable or disable by rk_atags
ec75791 static ta: support delete file from user ta
939cf88 static ta: support check cpu was replaced
Change-Id: Ia1e21a7272425bbf776b48cda3cc55c0fd5a77b3
Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
build from optee commit in develop-rk3228 branch:
d65a69f ddr: rk3288: add ddr_wait_vop_finish() in _ddr_adjust_config()
update feature:
d65a69f ddr: rk3288: add ddr_wait_vop_finish() in _ddr_adjust_config()
aa67a2b rockchip: flush all cache when cpu off
7a43c16 plat-rockchip: config: remove RK3368 related code
6c02489 scripts: optimize build scripts
805c30d scripts: add checkbuild.sh to build all platforms
Change-Id: I2cf6051caac47e77d6f53e56745353a659e24522
Signed-off-by: Zhihuan He <huan.he@rock-chips.com>
update feature:
a176f58 coos: rk3368: update bl30 version to v2.16 20191108
3ca0587 coos: rk3368: add DDR 2T mode control
ecbd739 coos: rk3368: set pll bypass if this pll was in power-down
Change-Id: I84a61a550980bc46234649a620c0dc34e36f319f
Signed-off-by: Zhihuan He <huan.he@rock-chips.com>
Fixes: 5d13e0b3dc04c
("rk3399pro: sync the same version with rk3399")
Change-Id: I173edabedcfc7adba9390430fca58b56dc414414
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
form commit 29450d8f7aac0220e25b759833553b22ff1311c2
update version to v2.57
Change-Id: I73aab87d936a15bf80ebf3e81fce8212207a45c1
Signed-off-by: Yifeng Zhao <zyf@rock-chips.com>
form commit 29450d8f7aac0220e25b759833553b22ff1311c2
update version to v2.57
Change-Id: I66d2bcbf0ecab674aed79d767660558020818296
Signed-off-by: Yifeng Zhao <zyf@rock-chips.com>
Base on U-Boot next-dev branch:
(5e817a0 tools: rockchip: resource_tool: add sha1 for file entry)
Change-Id: Ife061cabacab488dbecf2a3245d58cc660091dbd
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Update the content as below:
rk3399pro bl31 update to v1.30
rk3399pro miniloader/usbplug to v1.19
Change-Id: Ie25bd052c813040795854d5baea8f85e8b349163
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
from commit: 2a66b1c1891c77d08008850e672ecf563e7f27aa
Change-Id: I0810dc54f4ed6b8621b83d0fe79ff336df99e57c
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
from commit: 82ea4c8760db0544d4fed862260c5caddc92cf14
remove SPI Nand 4 bbt reserved block for open source framwork
Change-Id: I28fd631ed4f72c77a055bb2e0f8080369add5d45
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
build from:
c754b0d Version: DDR Version 1.24 20191016
update feature:
5ed0e6d lpddr4: add support multi frequency
1eb26fb RK3399: ddr: support choice uart by g_uart_info
Change-Id: Iaa89d141245904fdf524231fce9b8d3bff3be800
Signed-off-by: YouMin Chen <cym@rock-chips.com>
from commit: b94d56a72dda883dce5cb67e3c3fe0501f1b3930
Reverve 8 phy block for IDB to match with FTL reserved block
Change-Id: I399db156745aa2af7ff0d0b08b3ffc06caa26b0f
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
build from:
c754b0d Version: DDR Version 1.24 20191016
update feature:
5ed0e6d lpddr4: add support multi frequency
1eb26fb RK3399: ddr: support choice uart by g_uart_info
Change-Id: I128678613bd2eb3fcfe857cab9af63a6ed2786ed
Signed-off-by: YouMin Chen <cym@rock-chips.com>
We have deleted other uart bin file.If you want to generate other uart
bin file, please use ./tools/ddrbin_tool as follow:
1. modify "ddrbin_param.txt", choose ddr frequency, uart info.
2. run "ddrbin_tool" with argument 1: ddrbin_param.txt, argument 2: ddr
bin file.
build from:
ec2214e rockchip: rk3308: dram_init: updata to version 1.29
Update feature:
b1df665 drivers: ram: rockchip: rk3308: set phy dll delay
in different freq
73cb0bb drivers: ram: rockchip: rk3308: reduce ddr.bin size
a83ae48 drivers: ram: rockchip: rk3308: disable ddr standby
if disable sr or pd
0eb4bef drivers: ram: rockchip: rk3308: remove CONFIG_RK3308_ODT_ENABLE
245b957 rockchip: rk3308: dram_init: add surpport uart0~uart4 iomux
Change-Id: I7b84fa65f2671a348a36ea0529dcbcf518d452b5
Signed-off-by: Zhihuan He <huan.he@rock-chips.com>
from commit: I90d1f648b68a01ee125a045907fee9d3eec2129a
1.Remove Nor vendor partition
2.Support SPI Nor backup GPT
Change-Id: I00dc03d483e023128a80016cfbf5cfd41eed5f76
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
from commit: 2d08d469508ef9890e8f85e1a2ae3e94655c8602
invalid icache before run bl31
Change-Id: I65e35f54cc44daf5ba2684e96d3e726bd915ba9c
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
tool version: v1.00 20190920
This tool support modifying ddr frequency and uart infomation.
See tools/ddrbin_tool_user_guide.txt for more detail.
Change-Id: I1d634395c3cb0635a61fe8f227242523b926cd1b
Signed-off-by: Tang Yun ping <typ@rock-chips.com>
Build from commit:
30f1405 plat: rk3308: change BL31 offset from 0x10000 to 0x40000 on AArch64
Update feature:
30f1405 plat: rk3308: change BL31 offset from 0x10000 to 0x40000 on AArch64
Change-Id: If6039c5daf6e1a14f0fd145330a79c7b6050c5ad
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Build from ATF commit:
ca3dd02 plat: px30: set all region as secure to all master
update feature:
ca3dd02 plat: px30: set all region as secure to all master
a9dd46e plat: px30: change bl31_base to 0x40000
31ff1d0 plat: rockchip: set "plat_uart_base=0" if uart disable
Change-Id: Icfb591a14440257aa9b84ce4e9da0c9d7892d1fb
Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
Build from ATF commit:
ca3dd02 plat: px30: set all region as secure to all master
update feature:
ca3dd02 plat: px30: set all region as secure to all master
a9dd46e plat: px30: change bl31_base to 0x40000
31ff1d0 plat: rockchip: set "plat_uart_base=0" if uart disable
Change-Id: Ie0db861255ab5f0507ee91302ef23d9dbd175f70
Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
from commit: 32687efbfe62f4a38c6871133338c92c8381c227
1.src: platform rk3308: add icache clean
Change-Id: If70d017e08eebfcd314864fbcabb8f45c7d86653
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
from commit: 72205102d1643973a7ec05064b2e31982bd6a9f9
1.add new SPI flash GD5F2GQ5UEYIG
Change-Id: Ic9d395db6e43c33815a2ce07faf96bd906644ecf
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
