build from optee commit:
cf6a4d8 arm: sm: [bugfix] save/restore fiq core registers
update features:
fix reboot crash due to fiq data abort in OP-TEE
Change-Id: I09af898ebd74fe69f0fe9e05b2938a32ec4d8858
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
build from optee commit:
ad4b731 SVP: Fix last commit complile error.
update feature:
d0af79f SVP: Add an api to copy secure buffer.
5f837e7 fix compile bug when not define CFG_OTP_SUPPORT
0d52bd6 syscall: fixed bugs
8e2704c syscall: add a new syscall interface.
open CFG_TA_DRM configure and delete memblock_enable 3228H
Change-Id: I7e3d8a17fcfe5c0f400daa5d7c7356ce759a6099
Signed-off-by: Rimon Xu <rimon.xu@rock-chips.com>
This reverts commit 81ceebdf5a73e2e14facb7ad082032149f81fecd.
The latest bl32 bin has already merged the SVP functions,
so there's no need to use the macro CONFIG_MERGER_TRUSTIMAGE_DRM any more.
Change-Id: I2b87a9591e9ac1711319c155fd37df23f60cbf65
Signed-off-by: willam.wei <willam.wei@rock-chips.com>
Build from optee commit:
0d867b1 rk3288: suspend: only set arm_int_wkup_en and enable global_int_dis
update features:
1) 0d867b1 rk3288: suspend: only set arm_int_wkup_en and enable global_int_dis
2) 60b9e9a plat-rockchip: fix bugs of function "v7_flush_dcache_all"
3) 2bc8f7b plat-rockchip: rk3288: fix only one ddr channel's bug
Change-Id: Ic88fe4b630f019ff536ce2cb33ed3800141afd22
Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
support only one channel(channel_a) have connect DRAM.
Change-Id: If8941b195113d50324377208ddde24409f5a777f
Signed-off-by: YouMin Chen <cym@rock-chips.com>
build from optee commit:
c49f3d syscall: fixed bugs
update feature for rk3126:
77b1ba static ta: fix cflag when read and write
eaed6d static ta: not to creat file when read file.
993d9b static ta: set flag when uboot jump into kernel.
Change-Id: I5880b5e971fe9d744d7e22c6166ff46c8f1d1234
Signed-off-by: Hisping Lin <hisping.lin@rock-chips.com>
build from optee commit:
93e8858 rk322x: update version to 1.9
update features:
60b9e9a plat-rockchip: fix bugs of function "v7_flush_dcache_all"
dd3774b SVP: add seure video path
58cf1f4 rk3228 & rk3288: fix incorrect memblock config
32bbc9a rk3228: add a new static TA
299b44b rk322x: suspend: open mask clks that define in clk_ungt_msk
Change-Id: I055a889be3cb5519da028ae1bb86b0931a62c12f
Signed-off-by: Zhang Zhijie <zhangzj@rock-chips.com>
build from optee commit:
3ae8dd2 plat: rk312x: suspend: flash all dcache
update feature for rk312x:
1) plat: rk312x: suspend: flash all dcache
2) plat-rockchip: fix bugs of function "v7_flush_dcache_all"
3) plat: rk312x: cpu on/off: support cpu0 on
4) plat: rk312x: cpu on/off: add affinity_info
Change-Id: Ie10892861c95c7b8d1095ca8fb48a94cfe0b3524
Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
Both using grf_os_reg0 and pmu_sys_reg0 for flag into
maskrom device.
from commit:
6fbb2d5 rk3128: ddr: update to v2.07 20171109
Change-Id: Id52dcd7935fb74975f5713625754b809c5d0db29
Signed-off-by: Tang Yun ping <typ@rock-chips.com>
Both using grf_os_reg0 and pmu_sys_reg0 for flag into
maskrom device.
from commit:
1214cc2 rk3126: update to v2.09 20171109
Change-Id: Ib4ff97be3b2cb2fee3f258f3121148597324a201
Signed-off-by: Tang Yun ping <typ@rock-chips.com>
print info: DDR Version 1.10 20171106
This version fix dram type and dram cap possiblity detect incorrect.
from commit: e40ae20 rk322xh: ddr: fix dram training bug
Change-Id: I218049251c7fa052e044ede085fe36aa74c14aee
Signed-off-by: Tang Yun ping <typ@rock-chips.com>
built from ddr init project commit:
7c2ce8c version: release version of v1.06
update feature:
1) all ddr3 use 16bit, it can fix hynix DDR3 H5TC4G63CFR die's
starting up problem, and system stabilize problem.
Change-Id: I61d3410d12b7e924b2cb24cd28a2101fbaf7d49b
Signed-off-by: Hecanyang <hcy@rock-chips.com>
print info: "DDR Version v2.02 20170731"
This version fix bug of some dram type/dram bandwidth detect fail.
from commit:
aef516b rk3368: ddr: update ddr version to v2.02
Change-Id: I16cd5851a70d9a3d13aaa79162737fcf0a4ef7c1
Signed-off-by: Tang Yun ping <typ@rock-chips.com>
print info: "DDR Version V1.06 20171026"
1. add ddr2 init code to support ddr2.
2. fix bug of dram type detect fail.
3. fix bugs of dram bandwidth detect fail and some dram cap detect
fail when dram bandwidth equal to 16bit.
from commit:
08f6ed3 rk322x: ddr update to v1.06,fix some bugs when bw=16
Change-Id: I45bef1660f25e87a19f587663b8142d3e791af32
Signed-off-by: Tang Yun ping <typ@rock-chips.com>
built from optee commit: face623dceba59649815ffb36f32c3a7a0a28948
update feature:
rk3228H: add seure video path
1)support H264 HEVC VP9 VP8 MPEG2 MPEG4
2)add decrypt ta and video parser ta
3)support small vcodec_service, only support set/get region
Change-Id: I7fc600ec46baa579cfaf3d1b10f6646e59a38f23
Signed-off-by: willam.wei <willam.wei@rock-chips.com>
build from optee commit:
1997420 plat-rockchip: set CNTVOFF zero when cpu boot up
update feature for rk312x:
(1) support system reset;
(2) set CNTVOFF zero when cpu boot up.
Change-Id: I9f9d432df53093de31b40368f3b1b838239d7979
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
compile cmd:
make px5_kernel4.4_defconfig
make ARCHV=aarch64
ini, must modify this two file:
tools/rk_tools/RKBOOT/PX5KERNEL4.4MINIALL.ini
tools/rk_tools/RKTRUST/PX5KERNEL4.4TRUST.ini
Change-Id: Ib0c4f0885a895d005a42a723ff6aabe7023bc767
Signed-off-by: Jason Song <sxj@rock-chips.com>
build from optee commit: decbfaf1239a2d3452547fab6283e6d4adcdedde
update features:
1. support the suspend clock switch to 32k
2. fix bug for DDR3 DRAM side ODT disable
Change-Id: Ic4f492553e840f17c8a6066a60265aadd42d9398
Signed-off-by: shengfei Xu <xsf@rock-chips.com>
build from optee_os commit 438e3f7852917523e869334fba675c1f7fabf078
update features:
1. if #define CONFIG_MERGER_TRUSTIMAGE_DRM
the file "rk3399_bl32_tee_ta_DRM_v1.20.bin"
will be packed in trust.img
Change-Id: Ie4c698ef7ec4836b22618b6a9a7979b80d7e23a3
Signed-off-by: willam.wei <willam.wei@rock-chips.com>
build from optee commit:
50b9b79 rk322x: add system off by pull up rk805 sleep pin
Change-Id: I5ea9dd054879d0e0bded28b923fffa994dab9075
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
built from optee commit: 9f93abc55b1db63da07237f87db75e2c27620384
update features:
1.Ensure DPLL match dpll_rates_table
2.fix the error about qos save/restore
Change-Id: Ibecbf9402786153269b757b3df20c6d5c6bb1024
Signed-off-by: shengfei Xu <xsf@rock-chips.com>
built from ddr init project commit:
49df872 version: DDR Version 1.05 20170712
update feature:
1) fix customer DDR3 3GB with
channel a: col=10, row=16, cs=1, size = 2048MB
channel b: col=10, row=15, cs=1, size = 1024MB
2) support all 3GB and 1.5GB setting with DDR3
512Mx16bit and LPDDR3 single die with 8Gb case.
these rarely type of die was not consider before.
Change-Id: Ibdb5d758cc622a72672faff7069bd5efa85ce2e4
Signed-off-by: Hecanyang <hcy@rock-chips.com>
built from optee commit: 5cdf8deaa939a2cf23b1a20bbfd5460c93873404
update feature:
1)check mac/sn/stid's position has been writeen
2)add error correcting code
Change-Id: Ib436a55eb5a0c8f51158382155a8f0b4eef53da0
Signed-off-by: sean.huang <sean.huang@rock-chips.com>
