built from optee commit: face623dceba59649815ffb36f32c3a7a0a28948
update feature:
rk3228H: add seure video path
1)support H264 HEVC VP9 VP8 MPEG2 MPEG4
2)add decrypt ta and video parser ta
3)support small vcodec_service, only support set/get region
Change-Id: I7fc600ec46baa579cfaf3d1b10f6646e59a38f23
Signed-off-by: willam.wei <willam.wei@rock-chips.com>
build from optee commit:
1997420 plat-rockchip: set CNTVOFF zero when cpu boot up
update feature for rk312x:
(1) support system reset;
(2) set CNTVOFF zero when cpu boot up.
Change-Id: I9f9d432df53093de31b40368f3b1b838239d7979
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
compile cmd:
make px5_kernel4.4_defconfig
make ARCHV=aarch64
ini, must modify this two file:
tools/rk_tools/RKBOOT/PX5KERNEL4.4MINIALL.ini
tools/rk_tools/RKTRUST/PX5KERNEL4.4TRUST.ini
Change-Id: Ib0c4f0885a895d005a42a723ff6aabe7023bc767
Signed-off-by: Jason Song <sxj@rock-chips.com>
build from optee commit: decbfaf1239a2d3452547fab6283e6d4adcdedde
update features:
1. support the suspend clock switch to 32k
2. fix bug for DDR3 DRAM side ODT disable
Change-Id: Ic4f492553e840f17c8a6066a60265aadd42d9398
Signed-off-by: shengfei Xu <xsf@rock-chips.com>
build from optee_os commit 438e3f7852917523e869334fba675c1f7fabf078
update features:
1. if #define CONFIG_MERGER_TRUSTIMAGE_DRM
the file "rk3399_bl32_tee_ta_DRM_v1.20.bin"
will be packed in trust.img
Change-Id: Ie4c698ef7ec4836b22618b6a9a7979b80d7e23a3
Signed-off-by: willam.wei <willam.wei@rock-chips.com>
build from optee commit:
50b9b79 rk322x: add system off by pull up rk805 sleep pin
Change-Id: I5ea9dd054879d0e0bded28b923fffa994dab9075
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
built from optee commit: 9f93abc55b1db63da07237f87db75e2c27620384
update features:
1.Ensure DPLL match dpll_rates_table
2.fix the error about qos save/restore
Change-Id: Ibecbf9402786153269b757b3df20c6d5c6bb1024
Signed-off-by: shengfei Xu <xsf@rock-chips.com>
built from ddr init project commit:
49df872 version: DDR Version 1.05 20170712
update feature:
1) fix customer DDR3 3GB with
channel a: col=10, row=16, cs=1, size = 2048MB
channel b: col=10, row=15, cs=1, size = 1024MB
2) support all 3GB and 1.5GB setting with DDR3
512Mx16bit and LPDDR3 single die with 8Gb case.
these rarely type of die was not consider before.
Change-Id: Ibdb5d758cc622a72672faff7069bd5efa85ce2e4
Signed-off-by: Hecanyang <hcy@rock-chips.com>
built from optee commit: 5cdf8deaa939a2cf23b1a20bbfd5460c93873404
update feature:
1)check mac/sn/stid's position has been writeen
2)add error correcting code
Change-Id: Ib436a55eb5a0c8f51158382155a8f0b4eef53da0
Signed-off-by: sean.huang <sean.huang@rock-chips.com>
Update bl30 to v2.14 20170510 to support kernel_4.4 ddrfreq.
from coos commit:
cf10c6c coos: rk3368: update bl30 version to v2.14 20170510
Change-Id: Iafdfb74be33fc7894b63ed2639cf8641af52814c
Signed-off-by: Tang Yun ping <typ@rock-chips.com>
build from optee commit:
5f82045 rk312x: ddr: fix the bug of clk gate restore in deidle port
Change-Id: I1ff7f87ae689b01a3363ac3f357c921070bd7656
Signed-off-by: Jianhong Chen <chenjh@rock-chips.com>
build from optee commit: fc0d7b0db652ee6293cffd6ff2c53be9f2318e00
update features:
1.clear SCTLR_V bit when cpu init
2.add CFG_OTP_SUPPORT and CFG_BCH_SUPPORT
3.config: move fs config from script to conf.mk, enable rpmb
4.set Non-Secure banked TTBCR to zero
Change-Id: I2d650cf33c8e7f09008d8b8614cc87c1cfc31923
Signed-off-by: Zhang Zhijie <zhangzj@rock-chips.com>
built from optee commit: 1bbea2a96513fd50aaaabf5f69d2af005af96e79
update feature:
1)rpmb: fix bug on read and change test key define.
2)libcrypto: optimize crypto lib for keystore but not
enable BoringSSL(don't need for now).
3)toolchain: update toolchain version to gcc5.3.
Change-Id: I8f5670590264020f85644233f3d8b3d74a0578ee
Signed-off-by: Zhang Zhijie <zhangzj@rock-chips.com>
build from optee commit: debc2d5
update features:
debc2d5 rockchip: sip: page number not larger than requested one means query
4ab8acc rockchip: system suspend: disable fiq_debugger
ebdd9c2 ddr: rk3288: using unify scanning frequency parameters
Change-Id: I4c985274f8f833a1be54ce35deae4a35c31aae2a
Signed-off-by: chenjh <chenjh@rock-chips.com>
Build from bl31 commit: 159eeff3185a92768427d31c2da7b7361dabd03e
update features:
Change ddr frequency with rk3399's private functions
The patch is the interim measures for changing ddr frequency.
Change-Id: I47dfb494677e0fe5321c9180e62d4b00fa57abfc
Signed-off-by: shengfei Xu <xsf@rock-chips.com>
build from optee commit: f23c4e0
update features:
(1) support system reset;
(2) fix rk3229 crash.
support generate both trust.img and trust_with_ta.img
Change-Id: I06e808e5b14a0b83a5d412f8c66688451e92f62e
Signed-off-by: chenjh <chenjh@rock-chips.com>
built from optee commit:
4ab8acc rockchip: system suspend: disable fiq_debugger
update features:
1) rockchip: system suspend: disable fiq_debugger
2) rk3126c: suspend: support ddr suspend and arm off
3) rk3126c: fix delay time of efuse driver
Change-Id: I12515deb9af973e6357eb790a45222b080d4678e
Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
built from optee commit:
0bd05ab RK3288: optee version update to v1.1
update features:
1) plat-rockchip: rk3288: flush(clean & invalidate) entire D-cache
2) rk3288: fix bus about ISRAM_CODE_BASE redefined
3) rk3288: add ddr change frequency function
4) rk3288: fiq_dfs: add fiq_dfs_stop_cpus for rk3288
5) plat-rockchip: rk3288: support the sleep mode config from kernel
6) rk3288: check the cpu is in WFI before resetting it
Change-Id: I042019b3aa73debbcb0bbd9aa352bf95a1632a8f
Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
