build from optee commit: debc2d5
update features:
debc2d5 rockchip: sip: page number not larger than requested one means query
4ab8acc rockchip: system suspend: disable fiq_debugger
ebdd9c2 ddr: rk3288: using unify scanning frequency parameters
Change-Id: I4c985274f8f833a1be54ce35deae4a35c31aae2a
Signed-off-by: chenjh <chenjh@rock-chips.com>
Build from bl31 commit: 159eeff3185a92768427d31c2da7b7361dabd03e
update features:
Change ddr frequency with rk3399's private functions
The patch is the interim measures for changing ddr frequency.
Change-Id: I47dfb494677e0fe5321c9180e62d4b00fa57abfc
Signed-off-by: shengfei Xu <xsf@rock-chips.com>
build from optee commit: f23c4e0
update features:
(1) support system reset;
(2) fix rk3229 crash.
support generate both trust.img and trust_with_ta.img
Change-Id: I06e808e5b14a0b83a5d412f8c66688451e92f62e
Signed-off-by: chenjh <chenjh@rock-chips.com>
built from optee commit:
4ab8acc rockchip: system suspend: disable fiq_debugger
update features:
1) rockchip: system suspend: disable fiq_debugger
2) rk3126c: suspend: support ddr suspend and arm off
3) rk3126c: fix delay time of efuse driver
Change-Id: I12515deb9af973e6357eb790a45222b080d4678e
Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
built from optee commit:
0bd05ab RK3288: optee version update to v1.1
update features:
1) plat-rockchip: rk3288: flush(clean & invalidate) entire D-cache
2) rk3288: fix bus about ISRAM_CODE_BASE redefined
3) rk3288: add ddr change frequency function
4) rk3288: fiq_dfs: add fiq_dfs_stop_cpus for rk3288
5) plat-rockchip: rk3288: support the sleep mode config from kernel
6) rk3288: check the cpu is in WFI before resetting it
Change-Id: I042019b3aa73debbcb0bbd9aa352bf95a1632a8f
Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
built from optee commit:
201e349 plat: rk312x: add ddr change frequency function
1)add ddr change frequency function
2)add wait_cpus_into_wfe support
Change-Id: Ic0e1c6606079d781e6c9b87169f76f6f41e1934e
Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
Build from optee commit: 2101c108ef41637b2036c172d4f5f8144afefe6e
Main features:
1.rk3368 platform init
2.optimize crypto lib to support keystore.
3.using BoringSSL to generate RSA&ECC key.
4.rpmb: change the test key to RK defines.
5.toolchain: update toolchain version to gcc5.3.
Change-Id: I49919c59eee71f6496ebc6fc054b251950bcc5bd
Signed-off-by: Zhang Zhijie <zhangzj@rock-chips.com>
Build from bl31 commit: 84d85e7
update features:
1.support optee
2.softrest is set to first reset
3.suspend: support arm off and logic power down
4.really close cpu's power domain if system power down cpu
Change-Id: If1586b801daf7f7a8ccab95ceda4e168ea98528c
Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
Build from optee commit: 2101c108ef41637b2036c172d4f5f8144afefe6e
Main features:
1.rk3399 platform init
2.optimize crypto lib to support keystore.
3.using BoringSSL to generate RSA&ECC key.
4.rpmb: change the test key to RK defines.
5.toolchain: update toolchain version to gcc5.3.
Change-Id: Ie1aa580516572561d5f59825b72e743953af1500
Signed-off-by: hisping <hisping.lin@rock-chips.com>
Build from optee commit:8e11b8008bccbe47eebdf7ddd6c2001d3508f702
Update features:
1.Optimize crypto lib to support keystore.
2.Using BoringSSL to generate RSA&ECC key.
3.Update some features to compatible with arm-trusted-firmware.
4.Enable soc sram and set exec.
Change-Id: I439c7527cee94de76a27e3d4567f6351098a15b4
Signed-off-by: Zhang Zhijie <zhangzj@rock-chips.com>
1. support 128MB and 256MB SLC NAND
2. support some new MLC NAND FLASH
Change-Id: I75442d8980da28f7be8ba394c65689623727d92b
Signed-off-by: Zhaoyifeng <zyf@rock-chips.com>
this version's ddr bin file can adapt to all ddr type,
and all capability, and 2 layer or 4 layer PCB
Change-Id: I0037d2461de159d9259560f4ed28ac8f2b6d4476
Signed-off-by: Hecanyang <hcy@rock-chips.com>
rk3368h can't compatible with rk3368, so revert back to:
commit: 9cf916e75707f65bfbfb50ddecb47908ca0d8ba4
Change-Id: I4687d96255cea186ce6e5d2bd006f87c7ca3883d
Signed-off-by: chenjh <chenjh@rock-chips.com>
