print info:
DDR Version V1.03 20201224
build from u-boot-ddr:
434fcab38a rk356x: ddr: ddr bin version update to v1.03 20201224
build command:
./make.sh rk3568
update feature:
ad78184260 rk356x: ddr: disable ca odt when freq smaller than 800
498c940405 rk356x: ddr: gating training logic for power saving
f1e7e8286d rk356x: ddr: fix phy 2 cs cmd switch bug
cd72792efa rk356x: ddr: msch div follow with ddr freq
3d038f9428 rk356x: ddr: fix some ddr bug
01d47d2a87 rk356x: ddr: ddr_freq match DPLL setting
30a7d012c0 rk356x: ddr: add cs2_3_ca_skew in rk3568_fsp_param
56dd70be24 rk356x: ddr: lp4x use lp4 inc file to reduce code size
7e665ae1e3 rk356x: ddr: fix bug of pucal set
e15c349125 rk356x: ddr: set diff cs rd/wr gap to 2
11d6a8467e rk356x: ddr: fix auto low power bug and en auto low power
41385de8e5 rk356x: ddr: adjust drv/odt info
400a568e95 rk356x: ddr: optimizing and fix some code bug
Signed-off-by: Tang Yun ping <typ@rock-chips.com>
Change-Id: I02774dfb739615f3e4653fb2638569037779bc27
print info:
DDR Version V1.03 20201224
build from u-boot-ddr:
434fcab38a rk356x: ddr: ddr bin version update to v1.03 20201224
build command:
./make.sh rk3568
update feature:
ad78184260 rk356x: ddr: disable ca odt when freq smaller than 800
498c940405 rk356x: ddr: gating training logic for power saving
f1e7e8286d rk356x: ddr: fix phy 2 cs cmd switch bug
cd72792efa rk356x: ddr: msch div follow with ddr freq
3d038f9428 rk356x: ddr: fix some ddr bug
01d47d2a87 rk356x: ddr: ddr_freq match DPLL setting
30a7d012c0 rk356x: ddr: add cs2_3_ca_skew in rk3568_fsp_param
56dd70be24 rk356x: ddr: lp4x use lp4 inc file to reduce code size
7e665ae1e3 rk356x: ddr: fix bug of pucal set
e15c349125 rk356x: ddr: set diff cs rd/wr gap to 2
11d6a8467e rk356x: ddr: fix auto low power bug and en auto low power
41385de8e5 rk356x: ddr: adjust drv/odt info
400a568e95 rk356x: ddr: optimizing and fix some code bug
Signed-off-by: Tang Yun ping <typ@rock-chips.com>
Change-Id: I0732103216b4990e0d3e2a013cd4a363562667e8
Build from rk_boot_all commit:
29eb64 src: platform: rv1126: Update to v1.15
Update feature:
Support new SPI flash
Change-Id: Ibc05db6f2dd9dc4e2d707e2cdb8583e1bcb40dc4
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Build from next-dev with command ./make.sh rk3568
on-commit:
(73f4e1977b tools: add tools for convert bmp to gray16 and saved as logo.img)
Signed-off-by: Wenping Zhang <wenping.zhang@rock-chips.com>
Change-Id: Ic4910ba40c5626d0910f052025f15d7571c0095f
build from next-dev:
bf803435 rockchip: rk3568: fixup cru node frequency
build command:
./make.sh rv1126
Change-Id: I0676403a3bba4662acf08af6a08ca65cb8149347
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
build from:
6c4c411 rockchip: rk3568: support system power off
update feature:
rockchip: rk3568: support system power off
Signed-off-by: shengfei Xu <xsf@rock-chips.com>
Change-Id: I50960ff4be211642c72173925e2cfa7fd0da016a
from commit: ee9c4ff1120d490ef8f
Support new spi flash
Change-Id: Ic6db4a7ba164cc1667dbf3a07d1a029c06129d70
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
build from:
c8dcae6 Do not undef emmc when wo_ftl enable
update feature:
Enable emmc
Change-Id: I3b67920c2d7873b9993bfb2ae8f77e4be1ae7b0e
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Build from rk_boot_all commit:
d5c3b6a rk3568: support usb phy reset funcion
update feature:
Enable BL32_BL33_ARM32
Change-Id: If42572c139561946f693fbced39ef08c834f9f02
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
build from:
d5c3b6a support usb phy reset funcion
update feature:
Support SPI flash.
Change-Id: Ibb5529521c72ca8ec085be06aefa454466d4a7ef
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
lib/boot_merger is build from lib/boot_merger.py and
it's required by RK3568.
It compabiles with old loader format.
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: Ib9ace18d5b3a7465322e3f128e2e1ccb9192f3cf
build from:
186b00109f rockchip: rk3568: place U-Boot at 10MB offset
build command:
./make.sh rk3568
update feature:
Support get U-Boot entry address by fit header info
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I6ee4143dd9469ba100ba328c0e34cbbcb0032d73
They are generated by boot_merger, mainly for debug.
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I286dbb1d32bafa4417f08761c93b7df74560bca0
build from:
625aefe rk3568: support logic power down
update feature:
support logic power down
Signed-off-by: shengfei Xu <xsf@rock-chips.com>
Change-Id: Iad036aea3f0d0d1e95d230e30d89514b9b9768f0
from commit: ee9c4ff1120d490ef8f
Support new spi flash
Change-Id: Idab6ab012253de381403c74b6684bef716b22695
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
built from ddr init project commit:
338a11e version: DDR Version 1.09 20201119
update feature:
d8f0436 rk3288: ddr: add g_2t_info to control 2T
Signed-off-by: Zhihuan He <huan.he@rock-chips.com>
Change-Id: If5a2655e1d5ed5688d98d873034a6d855a7e1ee3
build from:
d74725a rk3568: support system suspend/resume
update feature:
support system suspend/resume
Signed-off-by: shengfei Xu <xsf@rock-chips.com>
Change-Id: I45e0e0e3a393191d3b44f2571b8528af65ae1d22
Build from rk_boot_all commit:
f2292af049: rk3326: update version v1.28
update feature:
1. Using Hamming distance to determine the chip type saved in OTP.
2. support MYTC 3D TLC.
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Change-Id: I15d4a034d456e2323fc86a302cb59bd26e21978a
from commit: a19a67a6f4ed6c28fa3f
Support new spi flash
Change-Id: I91ca57a0d54b673fe44c4c79d96ae081246b1182
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Build from rk_boot_all commit:
a593123211 src: flash: Change to reserve 8 blks for IDB without FTL
Update feature:
Change to reserve 8 blks for IDB without FTL
Change-Id: I69f1341a3569acbb9542bdb68de91b421d8f34fc
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
build from next-dev:
507e690 lib: rsa-verify: require np/c factor if using hardware decrypt
build command:
CONFIG_SPL_KERNEL_BOOT=y
for lp3 bin, CONFIG_ROCKCHIP_TPL_INIT_DRAM_TYPE need set to 6.
default CONFIG_ROCKCHIP_DRAM_EXTENDED_TEMP_SUPPORT=n, if you need
extended temperature bin, you need enable "CONFIG_ROCKCHIP_DRAM\
_EXTENDED_TEMP_SUPPORT", then rebuild uboot.
./make.sh rv1126 && ./make.sh tpl.
update feature:
1)ddr3 16bit support
2)optimizing ddr performance for bandwidth 16.
Change-Id: I5293dbadd36e32ae4c95eed2ca98f7a78de12426
Signed-off-by: Tang Yun ping <typ@rock-chips.com>
