Build from:
5dc6490a60 drivers: ram: rv1106: Initial version v1.06 20220509
(https://10.10.10.29/c/rk/ubd/+/145841/42)
Update feature:
1. Set defalut pack to QFN
2. Add 528MHz of DDR3 (Config 528MHz with ddrbin_tool)
3. Do not print warning when read eye trn flag is high, because
it is easy to happen at low freq
Signed-off-by: Wesley Yao <wesley.yao@rock-chips.com>
Change-Id: I40ada0a143b7b0b561fcc88f0c24f88ec7b29b52
build from:
03d6779 updata to version v1.10 20220506
update feature:
5854a58 tool: support -g gen.txt to modify ddrbin file
f088447 updata to version v1.10 20220406
0d86ab0 tool: add eye scanning support
Signed-off-by: Zhihuan He <huan.he@rock-chips.com>
Change-Id: I6cf674398d64243513eebbe0025597ea2ebcaa96
Build from u-boot-ddr:
drivers: ram: rv1106: Initial version v1.05 20220425
(https://10.10.10.29/c/rk/u-boot-ddr/+/145841/41)
Update feature:
1. Read OTP to get pack
2. Adjust NOC ReadLatency of DDR3 924MHz & 1056MHz
3. Delete 324MHz & 396MHz of DDR2
4. Enable PVTPLL
5. Config DDR_GRF_CON1&2 for power consumption
6. QFN gets SI info from MACRO, BGA gets SI info from
loader_params.inc
7. Set reg_train_2t_mode, and fix reg_cmd_2t_mode to 0x7fffff
8. Exit read gate if detect error flag
9. Fix set of t_xs_x32, t_xs_abort_x32 and t_xs_fast_x32
10. wait_phy_pll_lock in ddr_set_rate()
11. Decrease delay between rkclk_ddr_reset(dram, 1, 1, 1, 1) and
rkclk_ddr_reset(dram, 1, 1, 1, 0)
12. Call dram_all_config and enable_low_power in post_init
13. Add delay when detect row
Signed-off-by: Wesley Yao <wesley.yao@rock-chips.com>
Change-Id: Ic125bf2081c01aafdd6ef473c9b2145d41337a66
Build from u-boot-ddr:
c44e2c2649 drivers: ram: rv1106: Initial version v1.02 20220330
(https://10.10.10.29/c/rk/u-boot-ddr/+/145841/37)
and change baudrate to 115200
Update feature:
Change baudrate to 115200
Signed-off-by: Wesley Yao <wesley.yao@rock-chips.com>
Change-Id: Ic18c28757ae38670e27e5a1a0f6cc94ba4271f27
from commit:
rk_boot_all: fb9f8e: src: spinor: Support new spiflash
update feature:
Support new spiflash
Change-Id: I634d9f1707da419bafa3bf8d42778c8e758fe7c7
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Build from u-boot-ddr:
c44e2c2649 drivers: ram: rv1106: Initial version v1.02 20220330
(https://10.10.10.29/c/rk/u-boot-ddr/+/145841/37)
Update feature:
c44e2c2649 drivers: ram: rv1106: Initial version v1.02 20220330
(https://10.10.10.29/c/rk/u-boot-ddr/+/145841/37)
1. Fix 328MHz to 324MHz, 664MHz to 660MHz, 784MHz to 780MHz
2. Fix ReadLatency of NOC (-50)
3. Delete DQ skew cfg of DDR2
4. Set DeviceSize of NOC
5. Fix PHY PLL set
6. Fix wrong calc of wrlvl_info.tdqss_min/max
7. Fix wrong set of tRFC
Signed-off-by: Wesley Yao <wesley.yao@rock-chips.com>
Change-Id: I78755018346355647a28e5b85ee2ee390c49605d
Build from ATF commit:
7380d9813 plat: rockchip: rk3588: dmc: configure sr_en and pd_en based on idle value
update feature:
7380d9813 plat: rockchip: rk3588: dmc: configure sr_en and pd_en based on idle value
fedf3922d plat: rockchip: rk3588: dmc: add support LPDDR5 frequency scan
9328b4ce3 plat: rockchip: rk3588: dmc: clrbit RD_CAL_MODE if rd deskew is 0
Change-Id: Id5c38d95b2f74a17c03c7b3ff04345ddc66c947b
Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
from commit:
rk_boot_all: 209c77: src: spinand: Add SNAND tag for spinand PC tools
Update feature:
src: spinand: Add SNAND tag for spinand PC tools
Change-Id: Id03fc440a9d987c974bce0736e4494b5e0e939d5
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Build from u-boot-ddr:
0cc2c5d0bd drivers: ram: rv1106: Initial version v1.01 20220325
(https://10.10.10.29/c/rk/u-boot-ddr/+/145841/33)
Update feature:
0cc2c5d0bd drivers: ram: rv1106: Initial version v1.01 20220325
(https://10.10.10.29/c/rk/u-boot-ddr/+/145841/33)
1. Fix wrong calc of ddrconf, which ignore col
2. Do not init UART2 when in UART download
3. Fix wrong of memcpy of NOC
4. Fix wrong of update_dq_tx_skew/update_dq_tx_skew
5. Fix wrong of Disable PVT
6. Enable 2T of PHY_REG 0x1c
7. Return error if changing freq fail
Signed-off-by: Wesley Yao <wesley.yao@rock-chips.com>
Change-Id: I4e564b8322623834d8e117efd4dc1387f66fbffa
Build from ATF commit:
edf5c3fbb plat: px30-s:workaround LP3 can not open cs1 odt in wr train
Update feature:
edf5c3fbb plat: px30-s:workaround LP3 can not open cs1 odt in wr train
05922004b plat: px30-s: suspend: remove ddr_sr_fix_clk_phase() func
c088d3cc9 plat: px30-s: dram: remove phy dfi low power set
aa70ad066 plat: px30: don't init stimer1 if stimer1 is enabled
2877a2c9e plat: px30: support vdd_log off in suspend
Signed-off-by: Zhihuan He <huan.he@rock-chips.com>
Change-Id: I0436f3141234820fd31f959f122b1db1cd60d746
Build from ATF commit:
edf5c3fbb plat: px30-s:workaround LP3 can not open cs1 odt in wr train
Update feature:
edf5c3fbb plat: px30-s:workaround LP3 can not open cs1 odt in wr train
05922004b plat: px30-s: suspend: remove ddr_sr_fix_clk_phase() func
c088d3cc9 plat: px30-s: dram: remove phy dfi low power set
aa70ad066 plat: px30: don't init stimer1 if stimer1 is enabled
2877a2c9e plat: px30: support vdd_log off in suspend
Signed-off-by: Zhihuan He <huan.he@rock-chips.com>
Change-Id: I6db79ea74891ee56c1f886eeb749c7b4ad308aad
Build from ATF commit:
6a656152a plat: rk3588: save/restore all GICR in suspend
update feature:
6a656152a plat: rk3588: save/restore all GICR in suspend
9ae9e1a3f plat: rk3588: hdmirx: Speed up stopping CPUs
0b9f28efc plat: rockchip: rk3588: Add HDMIRX_HDMI interrupt handler
b604a56ff rockchip: support stop_cpu_fast function
021f3e1d6 plat: rk3588: don't flash cache in stop cpu
93e449183 plat: rk3588: enable EHF
302a312d3 plat: rk3588: mask all irqs before entry into opteed
fc6a6b092 rockchip: plat_pm: add functions for cpu on/suspend resume
0c6866c6d plat: rk3588: support EHF and SDEI
ab808d19f plat: rockchip: support config a fiq
c0152bd35 opteed: Mask non-secure interrupts if the cpus will be off
Change-Id: I7e37c17087a783ea8ab22bb598d5b36c0eef597c
Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
Build from OPTEE commit in develop-next branch:
4167319d3 core: tee: recreate dirf.db if open dirf.db fail
Update features:
4167319d3 core: tee: recreate dirf.db if open dirf.db fail
b61fa300d scripts: commit_bin: intercept the first 8 characters for LAST_CM
91c4147e7 pta: crypto_service: change some return code to be accurate
d40f7e8a8 drivers: crypto: clk: rv1126: fix the clock enablement logic
Signed-off-by: Hisping Lin <hisping.lin@rock-chips.com>
Change-Id: I2ec32c7094a57f8d7913eff935e4172abeac634f
Build from OPTEE commit in develop-next branch:
4167319d3 core: tee: recreate dirf.db if open dirf.db fail
Update features:
4167319d3 core: tee: recreate dirf.db if open dirf.db fail
b61fa300d scripts: commit_bin: intercept the first 8 characters for LAST_CM
91c4147e7 pta: crypto_service: change some return code to be accurate
3167e3733 drivers: rockchip: hal_crypto: mask lockstep interrupt
3f0f0b052 pta: support check oem otp key is written
48b7c13e2 pta: uboot_storedata_otp: modify parameter check
65daed964 pta: crypto_service: support oem otp key phys cipher
f5add58be core: TEE_GenerateKey support RSA key e = 3
Signed-off-by: Hisping Lin <hisping.lin@rock-chips.com>
Change-Id: Ia5c0776c1f207814a19095bfa5fda1f1f369902d
Build from OPTEE commit in develop-next branch:
4167319d3 core: tee: recreate dirf.db if open dirf.db fail
Update features:
4167319d3 core: tee: recreate dirf.db if open dirf.db fail
b61fa300d scripts: commit_bin: intercept the first 8 characters for LAST_CM
8e053a881 rockchip: remove duplicate definitions for toybrick seed
3f0f0b052 pta: support check oem otp key is written
9af9076b0 rockchip: sys_ctrl: move sys ctrl code to common/ dir
48b7c13e2 pta: uboot_storedata_otp: modify parameter check
65daed964 pta: crypto_service: support oem otp key phys cipher
60973cf4d drivers: crypto: hal: add crypto calc with phys addr
f5add58be core: TEE_GenerateKey support RSA key e = 3
af506d32e ta verify: close default key for sign ta
b05135511 pta: rk_os_service: support R&W oem hardware read otp
50cc53fd1 pta: support R&W oem non-secure otp
Signed-off-by: Hisping Lin <hisping.lin@rock-chips.com>
Change-Id: I738d31d3b329a0f6259d2546856d0599fd1e8089
Build from OPTEE commit in develop-next branch:
4167319d3 core: tee: recreate dirf.db if open dirf.db fail
Update features:
4167319d3 core: tee: recreate dirf.db if open dirf.db fail
b61fa300d scripts: commit_bin: intercept the first 8 characters for LAST_CM
8e053a881 rockchip: remove duplicate definitions for toybrick seed
91c4147e7 pta: crypto_service: change some return code to be accurate
3167e3733 drivers: rockchip: hal_crypto: mask lockstep interrupt
3f0f0b052 pta: support check oem otp key is written
9af9076b0 rockchip: sys_ctrl: move sys ctrl code to common/ dir
48b7c13e2 pta: uboot_storedata_otp: modify parameter check
65daed964 pta: crypto_service: support oem otp key phys cipher
7a0581630 scripts: commit_bin: support more platforms
f5add58be core: TEE_GenerateKey support RSA key e = 3
Signed-off-by: Hisping Lin <hisping.lin@rock-chips.com>
Change-Id: Icafc92b96494b0005a9663578b240b817c5a2bac
Build from OPTEE commit in develop-next branch:
4167319d3 core: tee: recreate dirf.db if open dirf.db fail
Update features:
4167319d3 core: tee: recreate dirf.db if open dirf.db fail
b61fa300d scripts: commit_bin: intercept the first 8 characters for LAST_CM
8e053a881 rockchip: remove duplicate definitions for toybrick seed
91c4147e7 pta: crypto_service: change some return code to be accurate
3167e3733 drivers: rockchip: hal_crypto: mask lockstep interrupt
3f0f0b052 pta: support check oem otp key is written
9af9076b0 rockchip: sys_ctrl: move sys ctrl code to common/ dir
48b7c13e2 pta: uboot_storedata_otp: modify parameter check
65daed964 pta: crypto_service: support oem otp key phys cipher
f5add58be core: TEE_GenerateKey support RSA key e = 3
Signed-off-by: Hisping Lin <hisping.lin@rock-chips.com>
Change-Id: I3f52db2bbfe52310a8798607f30da904ed96ebb7
Build from OPTEE commit in develop-next branch:
4167319d3 core: tee: recreate dirf.db if open dirf.db fail
Update features:
4167319d3 core: tee: recreate dirf.db if open dirf.db fail
b61fa300d scripts: commit_bin: intercept the first 8 characters for LAST_CM
91c4147e7 pta: crypto_service: change some return code to be accurate
d40f7e8a8 drivers: crypto: clk: rv1126: fix the clock enablement logic
3167e3733 drivers: rockchip: hal_crypto: mask lockstep interrupt
Signed-off-by: Hisping Lin <hisping.lin@rock-chips.com>
Change-Id: I07fc6e96c654f16c7ade1fed6dd513d86a0f52f1
from commit:
rk_boot_all: e48799: src: spinor: Support 4KB erase aligned
update feature:
Support spinor 4KB erase aligned
Change-Id: Id0fc2751744a7ff1555e919623bc5b57cb650120
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
