0ebdeb8e2b5762ad5788e28c3c221a8c083b39b3
Amend msch ddrconfig register write error and make sure row numbers configure in msch is equal to row numbers configure in ddr controller Change-Id: I03f673075ffc68f177a65e08a50896144eda1b4b Signed-off-by: Tang Yun ping <typ@rock-chips.com>
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