Hecanyang 5b275a99b0 ddr: DDR Version 1.00 20160530
2GB/1cs per channel, ddr init error.
fix this bug to support 2GB/1cs per channel.
2GB/1cs that is: row=16, col=10, bank=3, bw=2, cs=1

Change-Id: I222d1615d3df2c01312a04e5e0beab96fc1c2354
Signed-off-by: Hecanyang <hcy@rock-chips.com>
2016-05-30 17:16:48 +08:00
2016-05-30 17:16:48 +08:00
2016-05-30 17:16:48 +08:00
2013-09-11 15:12:57 +08:00
Description
Firmware and Tool Binarys
172 MiB
Languages
Python 74.2%
Shell 25.8%