Tang Yun ping
90dec21c9a
rk3506: ddr: update ddrbin to v1.06
bulid from:
d27ac532c4 dram_init: rk3506: update ddrbin to v1.06
update feature:
Fixed the SPI flash loading failure in SPL caused by
abnormal reset of hp_timer clock source
Signed-off-by: Tang Yun ping <typ@rock-chips.com>
Change-Id: Idbd304bd7bc50fa790f0d8e8218545d96ff533b4
2025-03-11 15:07:16 +08:00
..
2024-11-01 09:16:38 +08:00
2024-11-01 09:16:38 +08:00
2023-08-14 16:50:35 +08:00
2023-08-14 16:50:35 +08:00
2024-11-26 15:53:00 +08:00
2024-11-26 15:53:00 +08:00
2024-11-01 09:16:38 +08:00
2024-11-01 09:16:38 +08:00
2023-02-16 03:31:46 +00:00
2023-02-16 03:31:46 +00:00
2024-10-17 17:18:19 +08:00
2024-10-17 17:18:19 +08:00
2023-08-14 16:54:50 +08:00
2023-08-14 16:54:50 +08:00
2023-08-14 16:52:39 +08:00
2023-08-14 16:52:39 +08:00
2024-05-28 14:30:10 +08:00
2024-05-28 14:30:10 +08:00
2024-11-01 09:16:38 +08:00
2024-11-01 09:16:38 +08:00
2024-11-01 09:16:38 +08:00
2024-11-01 09:16:38 +08:00
2024-11-26 15:52:54 +08:00
2024-11-26 15:52:54 +08:00
2024-11-01 09:16:38 +08:00
2024-11-01 09:16:38 +08:00
2023-08-14 17:01:34 +08:00
2023-08-14 17:01:34 +08:00
2024-04-16 14:28:32 +08:00
2024-04-16 14:28:32 +08:00
2024-04-16 14:29:21 +08:00
2024-04-16 14:29:21 +08:00
2025-03-11 15:07:16 +08:00
2025-03-11 15:07:16 +08:00
2025-03-11 10:13:13 +08:00
2025-03-11 10:13:13 +08:00
2025-01-08 17:34:11 +08:00
2025-01-08 17:34:11 +08:00
2024-09-09 10:59:11 +08:00
2024-09-09 10:59:11 +08:00
2025-03-05 14:51:59 +08:00
2025-03-05 14:51:59 +08:00
2025-03-04 08:00:54 +00:00
2025-03-04 08:00:54 +00:00
2025-03-03 14:28:22 +08:00
2025-03-03 14:28:22 +08:00
2024-11-01 09:16:38 +08:00
2024-11-01 09:16:38 +08:00
2024-12-20 15:29:15 +08:00
2024-12-20 15:29:15 +08:00
2024-11-01 09:16:38 +08:00
2024-11-01 09:16:38 +08:00
2023-12-26 17:48:45 +08:00
2023-12-26 17:48:45 +08:00
2025-02-06 14:43:53 +08:00
2025-02-06 14:43:53 +08:00