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ufs: Sync possible UFS Quirks with Linux UFS driver
Sync u-boot UFS driver to add all possible UFS Quirks as supported by Linux UFS driver as well. Synced with include/ufs/ufshcd.h from Linux v6.11 release Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org> Tested-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com> Tested-by: Julius Lehmann <lehmanju@devpi.de> Link: https://lore.kernel.org/r/20240930-topic-ufs-enhancements-v3-9-58234f84ab89@linaro.org Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
This commit is contained in:
Bhupesh Sharma
committed by
Neil Armstrong
Neil Armstrong
parent
002afccdaf
commit
00c54af3ad
@@ -703,6 +703,169 @@ struct ufs_hba_ops {
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int (*phy_initialization)(struct ufs_hba *hba);
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};
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enum ufshcd_quirks {
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/* Interrupt aggregation support is broken */
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UFSHCD_QUIRK_BROKEN_INTR_AGGR = 1 << 0,
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/*
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* delay before each dme command is required as the unipro
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* layer has shown instabilities
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*/
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UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS = 1 << 1,
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/*
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* If UFS host controller is having issue in processing LCC (Line
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* Control Command) coming from device then enable this quirk.
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* When this quirk is enabled, host controller driver should disable
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* the LCC transmission on UFS device (by clearing TX_LCC_ENABLE
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* attribute of device to 0).
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*/
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UFSHCD_QUIRK_BROKEN_LCC = 1 << 2,
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/*
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* The attribute PA_RXHSUNTERMCAP specifies whether or not the
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* inbound Link supports unterminated line in HS mode. Setting this
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* attribute to 1 fixes moving to HS gear.
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*/
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UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP = 1 << 3,
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/*
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* This quirk needs to be enabled if the host controller only allows
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* accessing the peer dme attributes in AUTO mode (FAST AUTO or
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* SLOW AUTO).
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*/
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UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE = 1 << 4,
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/*
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* This quirk needs to be enabled if the host controller doesn't
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* advertise the correct version in UFS_VER register. If this quirk
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* is enabled, standard UFS host driver will call the vendor specific
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* ops (get_ufs_hci_version) to get the correct version.
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*/
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UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION = 1 << 5,
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/*
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* Clear handling for transfer/task request list is just opposite.
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*/
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UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR = 1 << 6,
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/*
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* This quirk needs to be enabled if host controller doesn't allow
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* that the interrupt aggregation timer and counter are reset by s/w.
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*/
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UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR = 1 << 7,
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/*
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* This quirks needs to be enabled if host controller cannot be
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* enabled via HCE register.
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*/
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UFSHCI_QUIRK_BROKEN_HCE = 1 << 8,
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/*
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* This quirk needs to be enabled if the host controller regards
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* resolution of the values of PRDTO and PRDTL in UTRD as byte.
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*/
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UFSHCD_QUIRK_PRDT_BYTE_GRAN = 1 << 9,
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/*
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* This quirk needs to be enabled if the host controller reports
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* OCS FATAL ERROR with device error through sense data
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*/
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UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR = 1 << 10,
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/*
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* This quirk needs to be enabled if the host controller has
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* auto-hibernate capability but it doesn't work.
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*/
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UFSHCD_QUIRK_BROKEN_AUTO_HIBERN8 = 1 << 11,
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/*
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* This quirk needs to disable manual flush for write booster
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*/
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UFSHCI_QUIRK_SKIP_MANUAL_WB_FLUSH_CTRL = 1 << 12,
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/*
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* This quirk needs to disable unipro timeout values
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* before power mode change
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*/
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UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING = 1 << 13,
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/*
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* This quirk needs to be enabled if the host controller does not
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* support UIC command
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*/
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UFSHCD_QUIRK_BROKEN_UIC_CMD = 1 << 15,
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/*
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* This quirk needs to be enabled if the host controller cannot
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* support physical host configuration.
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*/
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UFSHCD_QUIRK_SKIP_PH_CONFIGURATION = 1 << 16,
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/*
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* This quirk needs to be enabled if the host controller has
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* 64-bit addressing supported capability but it doesn't work.
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*/
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UFSHCD_QUIRK_BROKEN_64BIT_ADDRESS = 1 << 17,
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/*
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* This quirk needs to be enabled if the host controller has
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* auto-hibernate capability but it's FASTAUTO only.
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*/
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UFSHCD_QUIRK_HIBERN_FASTAUTO = 1 << 18,
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/*
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* This quirk needs to be enabled if the host controller needs
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* to reinit the device after switching to maximum gear.
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*/
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UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH = 1 << 19,
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/*
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* Some host raises interrupt (per queue) in addition to
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* CQES (traditional) when ESI is disabled.
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* Enable this quirk will disable CQES and use per queue interrupt.
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*/
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UFSHCD_QUIRK_MCQ_BROKEN_INTR = 1 << 20,
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/*
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* Some host does not implement SQ Run Time Command (SQRTC) register
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* thus need this quirk to skip related flow.
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*/
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UFSHCD_QUIRK_MCQ_BROKEN_RTC = 1 << 21,
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/*
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* This quirk needs to be enabled if the host controller supports inline
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* encryption but it needs to initialize the crypto capabilities in a
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* nonstandard way and/or needs to override blk_crypto_ll_ops. If
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* enabled, the standard code won't initialize the blk_crypto_profile;
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* ufs_hba_variant_ops::init() must do it instead.
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*/
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UFSHCD_QUIRK_CUSTOM_CRYPTO_PROFILE = 1 << 22,
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/*
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* This quirk needs to be enabled if the host controller supports inline
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* encryption but does not support the CRYPTO_GENERAL_ENABLE bit, i.e.
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* host controller initialization fails if that bit is set.
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*/
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UFSHCD_QUIRK_BROKEN_CRYPTO_ENABLE = 1 << 23,
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/*
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* This quirk needs to be enabled if the host controller driver copies
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* cryptographic keys into the PRDT in order to send them to hardware,
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* and therefore the PRDT should be zeroized after each request (as per
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* the standard best practice for managing keys).
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*/
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UFSHCD_QUIRK_KEYS_IN_PRDT = 1 << 24,
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/*
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* This quirk indicates that the controller reports the value 1 (not
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* supported) in the Legacy Single DoorBell Support (LSDBS) bit of the
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* Controller Capabilities register although it supports the legacy
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* single doorbell mode.
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*/
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UFSHCD_QUIRK_BROKEN_LSDBS_CAP = 1 << 25,
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};
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struct ufs_hba {
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struct udevice *dev;
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void __iomem *mmio_base;
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@@ -711,39 +874,7 @@ struct ufs_hba {
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u32 capabilities;
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u32 version;
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u32 intr_mask;
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u32 quirks;
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/*
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* If UFS host controller is having issue in processing LCC (Line
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* Control Command) coming from device then enable this quirk.
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* When this quirk is enabled, host controller driver should disable
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* the LCC transmission on UFS device (by clearing TX_LCC_ENABLE
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* attribute of device to 0).
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*/
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#define UFSHCD_QUIRK_BROKEN_LCC BIT(0)
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/*
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* This quirk needs to be enabled if the host controller has
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* 64-bit addressing supported capability but it doesn't work.
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*/
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#define UFSHCD_QUIRK_BROKEN_64BIT_ADDRESS BIT(1)
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/*
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* This quirk needs to be enabled if the host controller has
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* auto-hibernate capability but it's FASTAUTO only.
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*/
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#define UFSHCD_QUIRK_HIBERN_FASTAUTO BIT(2)
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/*
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* This quirk needs to be enabled if the host controller has
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* 64-bit addressing supported capability but it doesn't work.
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*/
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#define UFSHCD_QUIRK_BROKEN_64BIT_ADDRESS 0x2
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/*
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* This quirk needs to be enabled if the host controller has
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* auto-hibernate capability but it's FASTAUTO only.
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*/
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#define UFSHCD_QUIRK_HIBERN_FASTAUTO 0x4
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enum ufshcd_quirks quirks;
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/* Virtual memory reference */
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struct utp_transfer_cmd_desc *ucdl;
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