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Merge branch '2023-07-14-nuvoton-platform-updates'

Browse Source 
- A number of updates for the nuvoton family of platforms
This commit is contained in:
Tom Rini
2023-07-14 13:27:53 -04:00
parent b3bbad816e 4b7f29ff14
commit 089914ac5e
13 changed files with 134 additions and 29 deletions
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33
arch/arm/dts/nuvoton-npcm8xx-u-boot.dtsi
View File

@@ -289,6 +289,23 @@
status = "disable";
};
aes: aes@f0858000 {
compatible = "nuvoton,npcm845-aes";
reg = <0x0 0xf0858000 0x0 0x1000>,
<0x0 0xf0851000 0x0 0x1000>;
status = "disabled";
clocks = <&clk NPCM8XX_CLK_AHB>;
clock-names = "clk_ahb";
};
sha:sha@f085a000 {
compatible = "nuvoton,npcm845-sha";
reg = <0x0 0xf085a000 0x0 0x1000>;
status = "disabled";
clocks = <&clk NPCM8XX_CLK_AHB>;
clock-names = "clk_ahb";
};
apb {
serial0: serial@0 {
compatible = "nuvoton,npcm845-uart";
@@ -417,22 +434,6 @@
status = "disabled";
};
aes: aes@f0858000 {
compatible = "nuvoton,npcm845-aes";
reg = <0x0 0xf0858000 0x0 0x1000>,
<0x0 0xf0851000 0x0 0x1000>;
status = "disabled";
clocks = <&clk NPCM8XX_CLK_AHB>;
clock-names = "clk_ahb";
};
sha:sha@f085a000 {
compatible = "nuvoton,npcm845-sha";
reg = <0x0 0xf085a000 0x0 0x1000>;
status = "disabled";
clocks = <&clk NPCM8XX_CLK_AHB>;
clock-names = "clk_ahb";
};
};
};
pinctrl: pinctrl@f0800000 {

1
arch/arm/include/asm/arch-npcm8xx/gcr.h
View File

@@ -12,6 +12,7 @@
/* On-Chip ARBEL NPCM8XX VERSIONS */
#define ARBEL_Z1 0x00A35850
#define ARBEL_A1 0x04a35850
#define ARBEL_A2 0x08a35850
#define ARBEL_NPCM845 0x00000000
#define ARBEL_NPCM830 0x00300395
#define ARBEL_NPCM810 0x00000220

12
arch/arm/mach-npcm/npcm8xx/cpu.c
View File

@@ -68,6 +68,9 @@ int print_cpuinfo(void)
case ARBEL_A1:
printf("A1 @ ");
break;
case ARBEL_A2:
printf("A2 @ ");
break;
default:
printf("Unknown\n");
break;
@@ -92,7 +95,7 @@ int arch_cpu_init(void)
return 0;
}
static struct mm_region npcm_mem_map[1 + CONFIG_NR_DRAM_BANKS + 1] = {
static struct mm_region npcm_mem_map[] = {
{
/* DRAM */
.phys = 0x0UL,
@@ -109,6 +112,13 @@ static struct mm_region npcm_mem_map[1 + CONFIG_NR_DRAM_BANKS + 1] = {
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
{
.phys = 0x100000000UL,
.virt = 0x100000000UL,
.size = 0x80000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
},
{
/* List terminator */
0,

4
board/nuvoton/arbel_evb/Kconfig
View File

@@ -11,8 +11,8 @@ config SYS_CONFIG_NAME
config SYS_MEM_TOP_HIDE
hex "Reserved TOP memory"
default 0xB000000
default 0x0
help
Reserve memory for ECC/GFX/VCD/ECE.
Reserve memory for ECC/GFX/OPTEE/TIP/CP.
endif

70
board/nuvoton/arbel_evb/arbel_evb.c
View File

@@ -8,6 +8,17 @@
#include <asm/io.h>
#include <asm/arch/gcr.h>
#define SR_MII_CTRL_SWR_BIT15 15
#define DRAM_512MB_ECC_SIZE 0x1C000000ULL
#define DRAM_512MB_SIZE 0x20000000ULL
#define DRAM_1GB_ECC_SIZE 0x38000000ULL
#define DRAM_1GB_SIZE 0x40000000ULL
#define DRAM_2GB_ECC_SIZE 0x70000000ULL
#define DRAM_2GB_SIZE 0x80000000ULL
#define DRAM_4GB_ECC_SIZE 0xE00000000ULL
#define DRAM_4GB_SIZE 0x100000000ULL
DECLARE_GLOBAL_DATA_PTR;
int board_init(void)
@@ -18,12 +29,65 @@ int board_init(void)
int dram_init(void)
{
struct npcm_gcr *gcr = (struct npcm_gcr *)NPCM_GCR_BA;
uint64_t delta = 0ULL;
/*
* Get dram size from bootblock.
* The value is stored in scrpad_02 register.
* get dram active size value from bootblock.
* Value sent using scrpad_03 register.
* feature available in bootblock 0.0.6 and above.
*/
gd->ram_size = readl(&gcr->scrpad_b);
gd->ram_size = readl(&gcr->scrpad_c);
debug("%s: scrpad_c: %llx ", __func__, gd->ram_size);
if (gd->ram_size == 0) {
gd->ram_size = readl(&gcr->scrpad_b);
debug("%s: scrpad_b: %llx ", __func__, gd->ram_size);
} else {
gd->ram_size *= 0x100000ULL;
}
gd->bd->bi_dram[0].start = 0;
debug("ram_size: %llx ", gd->ram_size);
switch (gd->ram_size) {
case DRAM_512MB_ECC_SIZE:
case DRAM_512MB_SIZE:
case DRAM_1GB_ECC_SIZE:
case DRAM_1GB_SIZE:
case DRAM_2GB_ECC_SIZE:
case DRAM_2GB_SIZE:
gd->bd->bi_dram[0].size = gd->ram_size;
gd->bd->bi_dram[1].start = 0;
gd->bd->bi_dram[1].size = 0;
break;
case DRAM_4GB_ECC_SIZE:
gd->bd->bi_dram[0].size = DRAM_2GB_ECC_SIZE;
gd->bd->bi_dram[1].start = DRAM_4GB_SIZE;
gd->bd->bi_dram[1].size = DRAM_2GB_SIZE;
delta = DRAM_4GB_SIZE - DRAM_2GB_ECC_SIZE;
break;
case DRAM_4GB_SIZE:
gd->bd->bi_dram[0].size = DRAM_2GB_SIZE;
gd->bd->bi_dram[1].start = DRAM_4GB_SIZE;
gd->bd->bi_dram[1].size = DRAM_2GB_SIZE;
delta = DRAM_4GB_SIZE - DRAM_2GB_SIZE;
break;
default:
gd->bd->bi_dram[0].size = DRAM_1GB_SIZE;
gd->bd->bi_dram[1].start = 0;
gd->bd->bi_dram[1].size = 0;
break;
}
gd->ram_size -= delta;
return 0;
}
int dram_init_banksize(void)
{
dram_init();
return 0;
}

7
board/nuvoton/poleg_evb/poleg_evb.c
View File

@@ -6,6 +6,7 @@
#include <common.h>
#include <dm.h>
#include <env.h>
#include <asm/io.h>
#include <asm/arch/gcr.h>
#include <asm/mach-types.h>
@@ -19,6 +20,7 @@ int board_init(void)
int dram_init(void)
{
char value[32];
struct npcm_gcr *gcr = (struct npcm_gcr *)NPCM_GCR_BA;
int ramsize = (readl(&gcr->intcr3) >> 8) & 0x7;
@@ -44,5 +46,10 @@ int dram_init(void)
break;
}
if (gd->ram_size > 0) {
sprintf(value, "%ldM", (gd->ram_size / 0x100000));
env_set("mem", value);
}
return 0;
}

15
configs/arbel_evb_defconfig
View File

@@ -2,7 +2,8 @@ CONFIG_ARM=y
CONFIG_ARCH_NPCM=y
CONFIG_SYS_MALLOC_LEN=0x240000
CONFIG_SYS_MALLOC_F_LEN=0x1000
CONFIG_NR_DRAM_BANKS=1
CONFIG_TEXT_BASE=0x06208000
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_OFFSET=0x3C0000
CONFIG_ENV_SECT_SIZE=0x1000
@@ -22,6 +23,8 @@ CONFIG_BOOTCOMMAND="run common_bootargs; run romboot"
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=32
CONFIG_SYS_BOOTM_LEN=0x1400000
CONFIG_SYS_LOAD_ADDR=0x06208000
CONFIG_SYS_INIT_SP_ADDR=0x06208000
CONFIG_CMD_FUSE=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
@@ -86,3 +89,13 @@ CONFIG_USB_STORAGE=y
CONFIG_LIB_HW_RAND=y
CONFIG_SHA_HW_ACCEL=y
# CONFIG_EFI_LOADER is not set
CONFIG_TEE=y
CONFIG_OPTEE=y
CONFIG_TPM=y
CONFIG_TPM_V2=y
CONFIG_TPM2_FTPM_TEE=y
CONFIG_CMD_TPM=y
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_CMD_GPT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_CMD_PART=y

3
configs/poleg_evb_defconfig
View File

@@ -102,3 +102,6 @@ CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_WDT_NPCM=y
CONFIG_LIB_HW_RAND=y
CONFIG_SHA_HW_ACCEL=y
CONFIG_FIT=y
CONFIG_SHA256=y
CONFIG_SHA512=y

6
drivers/misc/npcm_host_intf.c
View File

@@ -50,9 +50,6 @@ static int npcm_host_intf_bind(struct udevice *dev)
const char *type;
int ret;
/* Release host wait */
setbits_8(SMC_CTL_REG_ADDR, SMC_CTL_HOSTWAIT);
syscon = syscon_regmap_lookup_by_phandle(dev, "syscon");
if (IS_ERR(syscon)) {
dev_err(dev, "%s: unable to get syscon, dev %s\n", __func__, dev->name);
@@ -93,6 +90,9 @@ static int npcm_host_intf_bind(struct udevice *dev)
regmap_update_bits(syscon, MFSEL1, MFSEL1_LPCSEL, MFSEL1_LPCSEL);
}
/* Release host wait */
setbits_8(SMC_CTL_REG_ADDR, SMC_CTL_HOSTWAIT);
return 0;
}

2
drivers/misc/npcm_otp.c
View File

@@ -33,7 +33,7 @@ static int npcm_otp_check_inputs(u32 arr, u32 word)
if (arr >= NPCM_NUM_OF_SA) {
if (IS_ENABLED(CONFIG_ARCH_NPCM8XX))
printf("\nError: npcm8XX otp includs only one bank: 0\n");
if (IS_ENABLED(CONFIG_ARCH_NPCM7XX))
if (IS_ENABLED(CONFIG_ARCH_NPCM7xx))
printf("\nError: npcm7XX otp includs only two banks: 0 and 1\n");
return -1;
}

3
drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c
View File

@@ -808,6 +808,9 @@ static bool is_gpio_persist(struct udevice *dev, uint bank)
status = npcm_get_reset_status();
dev_dbg(dev, "reset status: 0x%x\n", status);
if (status & PORST)
return false;
if (status & CORST)
regmap_read(priv->rst_regmap, CORSTC, &val);
else if (status & WD0RST)

5
include/configs/arbel.h
View File

@@ -7,12 +7,13 @@
#define __CONFIG_ARBEL_H
#define CFG_SYS_SDRAM_BASE 0x0
#define CFG_SYS_BOOTMAPSZ (20 << 20)
#define CFG_SYS_BOOTMAPSZ (30 << 20)
#define CFG_SYS_BOOTM_LEN (20 << 20)
#define CFG_SYS_INIT_RAM_ADDR CFG_SYS_SDRAM_BASE
#define CFG_SYS_INIT_RAM_SIZE 0x8000
/* Default environemnt variables */
#define CFG_EXTRA_ENV_SETTINGS "uimage_flash_addr=80200000\0" \
#define CFG_EXTRA_ENV_SETTINGS "uimage_flash_addr=80400000\0" \
"stdin=serial\0" \
"stdout=serial\0" \
"stderr=serial\0" \

2
include/configs/poleg.h
View File

@@ -27,6 +27,8 @@
"eth1addr=00:00:F7:A0:00:FD\0" \
"eth2addr=00:00:F7:A0:00:FE\0" \
"eth3addr=00:00:F7:A0:00:FF\0" \
"console=ttyS0,115200n8\0" \
"earlycon=uart8250,mmio32,0xf0000000\0" \
"common_bootargs=setenv bootargs earlycon=${earlycon} root=/dev/ram " \
"console=${console} mem=${mem} ramdisk_size=48000 basemac=${ethaddr}\0" \
"sd_prog=fatload mmc 0 10000000 image-bmc; cp.b 10000000 80000000 ${filesize}\0" \