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arm: dts: drop downstream IPQ4019 DTSI
We want to use OF_UPSTREAM on IPQ40XX as its well supported upstream, so lets drop our downstream DTSI. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Acked-by: Caleb Connolly <caleb.connolly@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
This commit is contained in:
Robert Marko
committed by
Caleb Connolly
Caleb Connolly
parent
12b6298251
commit
0a0fa4efce
@@ -1,202 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2019 Sartura Ltd.
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*
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* Author: Robert Marko <robert.marko@sartura.hr>
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*/
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/dts-v1/;
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#include "skeleton.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/clock/qcom,ipq4019-gcc.h>
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#include <dt-bindings/reset/qcom,ipq4019-reset.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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model = "Qualcomm Technologies, Inc. IPQ4019";
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compatible = "qcom,ipq4019";
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aliases {
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serial0 = &blsp1_uart1;
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spi0 = &blsp1_spi1;
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};
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reserved-memory {
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#address-cells = <0x1>;
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#size-cells = <0x1>;
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ranges;
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smem_mem: smem_region: smem@87e00000 {
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reg = <0x87e00000 0x080000>;
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no-map;
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};
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tz@87e80000 {
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reg = <0x87e80000 0x180000>;
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no-map;
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};
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};
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smem {
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compatible = "qcom,smem";
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memory-region = <&smem_mem>;
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};
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soc: soc {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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compatible = "simple-bus";
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gcc: clock-controller@1800000 {
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compatible = "qcom,gcc-ipq4019";
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reg = <0x1800000 0x60000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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bootph-all;
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};
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rng: rng@22000 {
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compatible = "qcom,prng";
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reg = <0x22000 0x140>;
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clocks = <&gcc GCC_PRNG_AHB_CLK>;
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status = "disabled";
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};
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soc_gpios: pinctrl@1000000 {
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compatible = "qcom,ipq4019-pinctrl";
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reg = <0x1000000 0x300000>;
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gpio-controller;
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gpio-count = <100>;
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gpio-bank-name="soc";
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#gpio-cells = <2>;
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bootph-all;
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};
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blsp1_uart1: serial@78af000 {
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compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
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reg = <0x78af000 0x200>;
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clock = <&gcc GCC_BLSP1_UART1_APPS_CLK>;
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bit-rate = <0xFF>;
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status = "disabled";
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bootph-all;
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};
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blsp1_spi1: spi@78b5000 {
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compatible = "qcom,spi-qup-v2.2.1";
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reg = <0x78b5000 0x600>;
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clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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bootph-all;
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};
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mdio: mdio@90000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "qcom,ipq4019-mdio";
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reg = <0x90000 0x64>;
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status = "disabled";
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ethphy0: ethernet-phy@0 {
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reg = <0>;
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};
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ethphy1: ethernet-phy@1 {
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reg = <1>;
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};
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ethphy2: ethernet-phy@2 {
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reg = <2>;
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};
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ethphy3: ethernet-phy@3 {
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reg = <3>;
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};
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ethphy4: ethernet-phy@4 {
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reg = <4>;
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};
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};
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usb3_ss_phy: ssphy@9a000 {
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compatible = "qcom,usb-ss-ipq4019-phy";
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#phy-cells = <0>;
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reg = <0x9a000 0x800>;
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reg-names = "phy_base";
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resets = <&gcc USB3_UNIPHY_PHY_ARES>;
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reset-names = "por_rst";
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status = "disabled";
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};
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usb3_hs_phy: hsphy@a6000 {
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compatible = "qcom,usb-hs-ipq4019-phy";
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#phy-cells = <0>;
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reg = <0xa6000 0x40>;
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reg-names = "phy_base";
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resets = <&gcc USB3_HSPHY_POR_ARES>, <&gcc USB3_HSPHY_S_ARES>;
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reset-names = "por_rst", "srif_rst";
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status = "disabled";
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};
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usb3: usb3@8af8800 {
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compatible = "qcom,dwc3";
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reg = <0x8af8800 0x100>;
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#address-cells = <1>;
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#size-cells = <1>;
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clocks = <&gcc GCC_USB3_MASTER_CLK>,
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<&gcc GCC_USB3_SLEEP_CLK>,
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<&gcc GCC_USB3_MOCK_UTMI_CLK>;
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clock-names = "master", "sleep", "mock_utmi";
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ranges;
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status = "disabled";
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dwc3@8a00000 {
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compatible = "snps,dwc3";
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reg = <0x8a00000 0xf8000>;
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phys = <&usb3_hs_phy>, <&usb3_ss_phy>;
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phy-names = "usb2-phy", "usb3-phy";
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dr_mode = "host";
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maximum-speed = "super-speed";
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snps,dis_u2_susphy_quirk;
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};
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};
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usb2_hs_phy: hsphy@a8000 {
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compatible = "qcom,usb-hs-ipq4019-phy";
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#phy-cells = <0>;
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reg = <0xa8000 0x40>;
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reg-names = "phy_base";
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resets = <&gcc USB2_HSPHY_POR_ARES>, <&gcc USB2_HSPHY_S_ARES>;
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reset-names = "por_rst", "srif_rst";
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status = "disabled";
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};
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usb2: usb2@60f8800 {
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compatible = "qcom,dwc3";
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reg = <0x60f8800 0x100>;
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#address-cells = <1>;
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#size-cells = <1>;
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clocks = <&gcc GCC_USB2_MASTER_CLK>,
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<&gcc GCC_USB2_SLEEP_CLK>,
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<&gcc GCC_USB2_MOCK_UTMI_CLK>;
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clock-names = "master", "sleep", "mock_utmi";
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ranges;
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status = "disabled";
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dwc3@6000000 {
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compatible = "snps,dwc3";
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reg = <0x6000000 0xf8000>;
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phys = <&usb2_hs_phy>;
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phy-names = "usb2-phy";
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dr_mode = "host";
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maximum-speed = "high-speed";
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snps,dis_u2_susphy_quirk;
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};
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};
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};
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};
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