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https://source.denx.de/u-boot/u-boot.git
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dts: th1520: Switch to upstream devicetree
Imply OF_UPSTREAM in platform Kconfig option and adapt existing boards to use the correct upstream devicetree paths. Signed-off-by: Yao Zi <ziyao@disroot.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
This commit is contained in:
Yao Zi
@@ -21,3 +21,4 @@ config THEAD_TH1520
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imply SPL_CPU
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imply SPL_OPENSBI
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imply SPL_LOAD_FIT
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imply OF_UPSTREAM
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@@ -12,7 +12,6 @@ dtb-$(CONFIG_TARGET_OPENPITON_RISCV64) += openpiton-riscv64.dtb
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dtb-$(CONFIG_TARGET_SIFIVE_UNLEASHED) += hifive-unleashed-a00.dtb
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dtb-$(CONFIG_TARGET_SIFIVE_UNMATCHED) += hifive-unmatched-a00.dtb
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dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb
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dtb-$(CONFIG_TARGET_TH1520_LPI4A) += th1520-lichee-pi-4a.dtb
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dtb-$(CONFIG_TARGET_XILINX_MBV) += xilinx-mbv32.dtb
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dtb-$(CONFIG_TARGET_XILINX_MBV) += xilinx-mbv64.dtb
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dtb-$(CONFIG_TARGET_XILINX_MBV) += xilinx-binman.dtb
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10
arch/riscv/dts/th1520-lichee-module-4a-u-boot.dtsi
Normal file
10
arch/riscv/dts/th1520-lichee-module-4a-u-boot.dtsi
Normal file
@@ -0,0 +1,10 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2025 Yao Zi <ziyao@disroot.org>
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*/
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#include "th1520-u-boot.dtsi"
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&{/memory@0} {
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bootph-pre-ram;
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};
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@@ -1,164 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
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*/
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/dts-v1/;
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#include "th1520.dtsi"
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/ {
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model = "Sipeed Lichee Module 4A";
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compatible = "sipeed,lichee-module-4a", "thead,th1520";
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aliases {
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ethernet0 = &gmac0;
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ethernet1 = &gmac1;
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};
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memory@0 {
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device_type = "memory";
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reg = <0x0 0x00000000 0x2 0x00000000>;
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bootph-pre-ram;
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};
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};
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&osc {
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clock-frequency = <24000000>;
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};
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&osc_32k {
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clock-frequency = <32768>;
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};
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&emmc {
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bus-width = <8>;
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max-frequency = <198000000>;
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mmc-ddr-1_8v;
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mmc-hs400-1_8v;
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mmc-hs400-enhanced-strobe;
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non-removable;
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no-sdio;
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no-sd;
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status = "okay";
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};
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&gmac0 {
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pinctrl-names = "default";
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pinctrl-0 = <&gmac0_pins>, <&mdio0_pins>;
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phy-handle = <&phy0>;
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phy-mode = "rgmii-id";
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status = "okay";
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};
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&gmac1 {
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pinctrl-names = "default";
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pinctrl-0 = <&gmac1_pins>;
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phy-handle = <&phy1>;
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phy-mode = "rgmii-id";
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status = "okay";
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};
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&mdio0 {
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phy0: ethernet-phy@1 {
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reg = <1>;
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};
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phy1: ethernet-phy@2 {
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reg = <2>;
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};
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};
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&padctrl0_apsys {
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gmac0_pins: gmac0-0 {
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tx-pins {
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pins = "GMAC0_TX_CLK",
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"GMAC0_TXEN",
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"GMAC0_TXD0",
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"GMAC0_TXD1",
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"GMAC0_TXD2",
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"GMAC0_TXD3";
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function = "gmac0";
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bias-disable;
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drive-strength = <25>;
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input-disable;
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input-schmitt-disable;
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slew-rate = <0>;
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};
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rx-pins {
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pins = "GMAC0_RX_CLK",
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"GMAC0_RXDV",
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"GMAC0_RXD0",
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"GMAC0_RXD1",
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"GMAC0_RXD2",
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"GMAC0_RXD3";
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function = "gmac0";
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bias-disable;
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drive-strength = <1>;
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input-enable;
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input-schmitt-disable;
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slew-rate = <0>;
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};
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};
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gmac1_pins: gmac1-0 {
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tx-pins {
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pins = "GPIO2_18", /* GMAC1_TX_CLK */
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"GPIO2_20", /* GMAC1_TXEN */
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"GPIO2_21", /* GMAC1_TXD0 */
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"GPIO2_22", /* GMAC1_TXD1 */
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"GPIO2_23", /* GMAC1_TXD2 */
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"GPIO2_24"; /* GMAC1_TXD3 */
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function = "gmac1";
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bias-disable;
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drive-strength = <25>;
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input-disable;
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input-schmitt-disable;
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slew-rate = <0>;
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};
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rx-pins {
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pins = "GPIO2_19", /* GMAC1_RX_CLK */
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"GPIO2_25", /* GMAC1_RXDV */
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"GPIO2_30", /* GMAC1_RXD0 */
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"GPIO2_31", /* GMAC1_RXD1 */
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"GPIO3_0", /* GMAC1_RXD2 */
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"GPIO3_1"; /* GMAC1_RXD3 */
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function = "gmac1";
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bias-disable;
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drive-strength = <1>;
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input-enable;
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input-schmitt-disable;
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slew-rate = <0>;
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};
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};
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mdio0_pins: mdio0-0 {
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mdc-pins {
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pins = "GMAC0_MDC";
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function = "gmac0";
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bias-disable;
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drive-strength = <13>;
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input-disable;
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input-schmitt-disable;
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slew-rate = <0>;
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};
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mdio-pins {
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pins = "GMAC0_MDIO";
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function = "gmac0";
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bias-disable;
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drive-strength = <13>;
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input-enable;
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input-schmitt-enable;
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slew-rate = <0>;
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};
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};
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};
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&sdio0 {
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bus-width = <4>;
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max-frequency = <198000000>;
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status = "okay";
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};
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27
arch/riscv/dts/th1520-lichee-pi-4a-u-boot.dtsi
Normal file
27
arch/riscv/dts/th1520-lichee-pi-4a-u-boot.dtsi
Normal file
@@ -0,0 +1,27 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2025 Yao Zi <ziyao@disroot.org>
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*/
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#include "th1520-lichee-module-4a-u-boot.dtsi"
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#include "thead-th1520-binman.dtsi"
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&clk {
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bootph-some-ram;
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};
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&padctrl0_apsys {
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bootph-some-ram;
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};
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&uart0_pins {
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bootph-some-ram;
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tx-pins {
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bootph-some-ram;
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};
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rx-pins {
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bootph-some-ram;
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};
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};
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@@ -1,33 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
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*/
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#include "th1520-lichee-module-4a.dtsi"
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#include "thead-th1520-binman.dtsi"
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/ {
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model = "Sipeed Lichee Pi 4A";
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compatible = "sipeed,lichee-pi-4a", "sipeed,lichee-module-4a", "thead,th1520";
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aliases {
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gpio0 = &gpio0;
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gpio1 = &gpio1;
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gpio2 = &gpio2;
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gpio3 = &gpio3;
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serial0 = &uart0;
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serial1 = &uart1;
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serial2 = &uart2;
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serial3 = &uart3;
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serial4 = &uart4;
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serial5 = &uart5;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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};
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&uart0 {
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status = "okay";
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};
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44
arch/riscv/dts/th1520-u-boot.dtsi
Normal file
44
arch/riscv/dts/th1520-u-boot.dtsi
Normal file
@@ -0,0 +1,44 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2025 Yao Zi <ziyao@disroot.org>
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*/
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&{/soc} {
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ddrc: ddrc@fffd000000 {
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compatible = "thead,th1520-ddrc";
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reg = <0xff 0xfd000000 0x0 0x1000000>,
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<0xff 0xfe000000 0x0 0x1000000>,
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<0xff 0xff000000 0x0 0x4000>,
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<0xff 0xff005000 0x0 0x1000>;
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reg-names = "phy-0", "phy-1", "ctrl", "sys";
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bootph-pre-ram;
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};
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};
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&cpus {
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bootph-pre-ram;
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};
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&c910_0 {
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bootph-pre-ram;
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};
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&c910_1 {
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bootph-pre-ram;
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};
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&c910_2 {
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bootph-pre-ram;
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};
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&c910_3 {
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bootph-pre-ram;
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};
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&clint {
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bootph-pre-ram;
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};
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&uart0 {
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bootph-pre-ram;
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};
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@@ -1,530 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2021 Alibaba Group Holding Limited.
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* Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
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*/
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#include <dt-bindings/clock/thead,th1520-clk-ap.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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/ {
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compatible = "thead,th1520";
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#address-cells = <2>;
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#size-cells = <2>;
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cpus: cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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bootph-pre-ram;
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timebase-frequency = <3000000>;
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c910_0: cpu@0 {
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compatible = "thead,c910", "riscv";
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device_type = "cpu";
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riscv,isa = "rv64imafdc";
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reg = <0>;
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bootph-pre-ram;
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i-cache-block-size = <64>;
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i-cache-size = <65536>;
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i-cache-sets = <512>;
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d-cache-block-size = <64>;
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d-cache-size = <65536>;
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d-cache-sets = <512>;
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next-level-cache = <&l2_cache>;
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mmu-type = "riscv,sv39";
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cpu0_intc: interrupt-controller {
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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};
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c910_1: cpu@1 {
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compatible = "thead,c910", "riscv";
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device_type = "cpu";
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riscv,isa = "rv64imafdc";
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reg = <1>;
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bootph-pre-ram;
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i-cache-block-size = <64>;
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i-cache-size = <65536>;
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i-cache-sets = <512>;
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d-cache-block-size = <64>;
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d-cache-size = <65536>;
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d-cache-sets = <512>;
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next-level-cache = <&l2_cache>;
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mmu-type = "riscv,sv39";
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cpu1_intc: interrupt-controller {
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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};
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c910_2: cpu@2 {
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compatible = "thead,c910", "riscv";
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device_type = "cpu";
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riscv,isa = "rv64imafdc";
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reg = <2>;
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bootph-pre-ram;
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i-cache-block-size = <64>;
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i-cache-size = <65536>;
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i-cache-sets = <512>;
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d-cache-block-size = <64>;
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d-cache-size = <65536>;
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d-cache-sets = <512>;
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next-level-cache = <&l2_cache>;
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mmu-type = "riscv,sv39";
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cpu2_intc: interrupt-controller {
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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};
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c910_3: cpu@3 {
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compatible = "thead,c910", "riscv";
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device_type = "cpu";
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riscv,isa = "rv64imafdc";
|
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reg = <3>;
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bootph-pre-ram;
|
||||
i-cache-block-size = <64>;
|
||||
i-cache-size = <65536>;
|
||||
i-cache-sets = <512>;
|
||||
d-cache-block-size = <64>;
|
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d-cache-size = <65536>;
|
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d-cache-sets = <512>;
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next-level-cache = <&l2_cache>;
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mmu-type = "riscv,sv39";
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cpu3_intc: interrupt-controller {
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compatible = "riscv,cpu-intc";
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interrupt-controller;
|
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#interrupt-cells = <1>;
|
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};
|
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};
|
||||
|
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l2_cache: l2-cache {
|
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compatible = "cache";
|
||||
cache-block-size = <64>;
|
||||
cache-level = <2>;
|
||||
cache-size = <1048576>;
|
||||
cache-sets = <1024>;
|
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cache-unified;
|
||||
};
|
||||
};
|
||||
|
||||
osc: oscillator {
|
||||
compatible = "fixed-clock";
|
||||
clock-output-names = "osc_24m";
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
osc_32k: 32k-oscillator {
|
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compatible = "fixed-clock";
|
||||
clock-output-names = "osc_32k";
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
aonsys_clk: clock-73728000 {
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <73728000>;
|
||||
clock-output-names = "aonsys_clk";
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
soc {
|
||||
compatible = "simple-bus";
|
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interrupt-parent = <&plic>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
plic: interrupt-controller@ffd8000000 {
|
||||
compatible = "thead,th1520-plic", "thead,c900-plic";
|
||||
reg = <0xff 0xd8000000 0x0 0x01000000>;
|
||||
interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>,
|
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<&cpu1_intc 11>, <&cpu1_intc 9>,
|
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<&cpu2_intc 11>, <&cpu2_intc 9>,
|
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<&cpu3_intc 11>, <&cpu3_intc 9>;
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
riscv,ndev = <240>;
|
||||
};
|
||||
|
||||
clint: timer@ffdc000000 {
|
||||
compatible = "thead,th1520-clint", "thead,c900-clint";
|
||||
reg = <0xff 0xdc000000 0x0 0x00010000>;
|
||||
bootph-pre-ram;
|
||||
interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
|
||||
<&cpu1_intc 3>, <&cpu1_intc 7>,
|
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<&cpu2_intc 3>, <&cpu2_intc 7>,
|
||||
<&cpu3_intc 3>, <&cpu3_intc 7>;
|
||||
};
|
||||
|
||||
uart0: serial@ffe7014000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0xff 0xe7014000 0x0 0x100>;
|
||||
bootph-pre-ram;
|
||||
interrupts = <36 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART0_PCLK>;
|
||||
clock-names = "buadclk", "apb_pclk";
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gmac1: ethernet@ffe7060000 {
|
||||
compatible = "thead,th1520-gmac", "snps,dwmac-3.70a";
|
||||
reg = <0xff 0xe7060000 0x0 0x2000>, <0xff 0xec004000 0x0 0x1000>;
|
||||
reg-names = "dwmac", "apb";
|
||||
interrupts = <67 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "macirq";
|
||||
clocks = <&clk CLK_GMAC_AXI>, <&clk CLK_GMAC1>;
|
||||
clock-names = "stmmaceth", "pclk";
|
||||
snps,pbl = <32>;
|
||||
snps,fixed-burst;
|
||||
snps,multicast-filter-bins = <64>;
|
||||
snps,perfect-filter-entries = <32>;
|
||||
status = "disabled";
|
||||
|
||||
mdio1: mdio {
|
||||
compatible = "snps,dwmac-mdio";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
gmac0: ethernet@ffe7070000 {
|
||||
compatible = "thead,th1520-gmac", "snps,dwmac-3.70a";
|
||||
reg = <0xff 0xe7070000 0x0 0x2000>, <0xff 0xec003000 0x0 0x1000>;
|
||||
reg-names = "dwmac", "apb";
|
||||
interrupts = <66 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "macirq";
|
||||
clocks = <&clk CLK_GMAC_AXI>, <&clk CLK_GMAC0>;
|
||||
clock-names = "stmmaceth", "pclk";
|
||||
snps,pbl = <32>;
|
||||
snps,fixed-burst;
|
||||
snps,multicast-filter-bins = <64>;
|
||||
snps,perfect-filter-entries = <32>;
|
||||
status = "disabled";
|
||||
|
||||
mdio0: mdio {
|
||||
compatible = "snps,dwmac-mdio";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
emmc: mmc@ffe7080000 {
|
||||
compatible = "thead,th1520-dwcmshc";
|
||||
reg = <0xff 0xe7080000 0x0 0x10000>;
|
||||
interrupts = <62 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk CLK_EMMC_SDIO>;
|
||||
clock-names = "core";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdio0: mmc@ffe7090000 {
|
||||
compatible = "thead,th1520-dwcmshc";
|
||||
reg = <0xff 0xe7090000 0x0 0x10000>;
|
||||
interrupts = <64 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk CLK_EMMC_SDIO>;
|
||||
clock-names = "core";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdio1: mmc@ffe70a0000 {
|
||||
compatible = "thead,th1520-dwcmshc";
|
||||
reg = <0xff 0xe70a0000 0x0 0x10000>;
|
||||
interrupts = <71 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk CLK_EMMC_SDIO>;
|
||||
clock-names = "core";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart1: serial@ffe7f00000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0xff 0xe7f00000 0x0 0x100>;
|
||||
interrupts = <37 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART1_PCLK>;
|
||||
clock-names = "buadclk", "apb_pclk";
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart3: serial@ffe7f04000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0xff 0xe7f04000 0x0 0x100>;
|
||||
interrupts = <39 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART3_PCLK>;
|
||||
clock-names = "buadclk", "apb_pclk";
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio2: gpio@ffe7f34000 {
|
||||
compatible = "snps,dw-apb-gpio";
|
||||
reg = <0xff 0xe7f34000 0x0 0x1000>;
|
||||
clocks = <&clk CLK_GPIO2>;
|
||||
clock-names = "bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
portc: gpio-controller@0 {
|
||||
compatible = "snps,dw-apb-gpio-port";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
ngpios = <32>;
|
||||
reg = <0>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <58 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio3: gpio@ffe7f38000 {
|
||||
compatible = "snps,dw-apb-gpio";
|
||||
reg = <0xff 0xe7f38000 0x0 0x1000>;
|
||||
clocks = <&clk CLK_GPIO3>;
|
||||
clock-names = "bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
portd: gpio-controller@0 {
|
||||
compatible = "snps,dw-apb-gpio-port";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
ngpios = <32>;
|
||||
reg = <0>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <59 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
padctrl1_apsys: pinctrl@ffe7f3c000 {
|
||||
compatible = "thead,th1520-pinctrl";
|
||||
reg = <0xff 0xe7f3c000 0x0 0x1000>;
|
||||
clocks = <&clk CLK_PADCTRL1>;
|
||||
thead,pad-group = <2>;
|
||||
};
|
||||
|
||||
gpio0: gpio@ffec005000 {
|
||||
compatible = "snps,dw-apb-gpio";
|
||||
reg = <0xff 0xec005000 0x0 0x1000>;
|
||||
clocks = <&clk CLK_GPIO0>;
|
||||
clock-names = "bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
porta: gpio-controller@0 {
|
||||
compatible = "snps,dw-apb-gpio-port";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
ngpios = <32>;
|
||||
reg = <0>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <56 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio1: gpio@ffec006000 {
|
||||
compatible = "snps,dw-apb-gpio";
|
||||
reg = <0xff 0xec006000 0x0 0x1000>;
|
||||
clocks = <&clk CLK_GPIO1>;
|
||||
clock-names = "bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
portb: gpio-controller@0 {
|
||||
compatible = "snps,dw-apb-gpio-port";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
ngpios = <32>;
|
||||
reg = <0>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <57 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
padctrl0_apsys: pinctrl@ffec007000 {
|
||||
compatible = "thead,th1520-pinctrl";
|
||||
reg = <0xff 0xec007000 0x0 0x1000>;
|
||||
clocks = <&clk CLK_PADCTRL0>;
|
||||
thead,pad-group = <3>;
|
||||
};
|
||||
|
||||
uart2: serial@ffec010000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0xff 0xec010000 0x0 0x4000>;
|
||||
interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART2_PCLK>;
|
||||
clock-names = "buadclk", "apb_pclk";
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
clk: clock-controller@ffef010000 {
|
||||
compatible = "thead,th1520-clk-ap";
|
||||
reg = <0xff 0xef010000 0x0 0x1000>;
|
||||
clocks = <&osc>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
timer0: timer@ffefc32000 {
|
||||
compatible = "snps,dw-apb-timer";
|
||||
reg = <0xff 0xefc32000 0x0 0x14>;
|
||||
clocks = <&clk CLK_PERI_APB_PCLK>;
|
||||
clock-names = "timer";
|
||||
interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
timer1: timer@ffefc32014 {
|
||||
compatible = "snps,dw-apb-timer";
|
||||
reg = <0xff 0xefc32014 0x0 0x14>;
|
||||
clocks = <&clk CLK_PERI_APB_PCLK>;
|
||||
clock-names = "timer";
|
||||
interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
timer2: timer@ffefc32028 {
|
||||
compatible = "snps,dw-apb-timer";
|
||||
reg = <0xff 0xefc32028 0x0 0x14>;
|
||||
clocks = <&clk CLK_PERI_APB_PCLK>;
|
||||
clock-names = "timer";
|
||||
interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
timer3: timer@ffefc3203c {
|
||||
compatible = "snps,dw-apb-timer";
|
||||
reg = <0xff 0xefc3203c 0x0 0x14>;
|
||||
clocks = <&clk CLK_PERI_APB_PCLK>;
|
||||
clock-names = "timer";
|
||||
interrupts = <19 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart4: serial@fff7f08000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0xff 0xf7f08000 0x0 0x4000>;
|
||||
interrupts = <40 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART4_PCLK>;
|
||||
clock-names = "buadclk", "apb_pclk";
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart5: serial@fff7f0c000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0xff 0xf7f0c000 0x0 0x4000>;
|
||||
interrupts = <41 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART5_PCLK>;
|
||||
clock-names = "buadclk", "apb_pclk";
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ddrc: ddrc@fffd000000 {
|
||||
compatible = "thead,th1520-ddrc";
|
||||
reg = <0xff 0xfd000000 0x0 0x1000000>,
|
||||
<0xff 0xfe000000 0x0 0x1000000>,
|
||||
<0xff 0xff000000 0x0 0x4000>,
|
||||
<0xff 0xff005000 0x0 0x1000>;
|
||||
reg-names = "phy-0", "phy-1", "ctrl", "sys";
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
timer4: timer@ffffc33000 {
|
||||
compatible = "snps,dw-apb-timer";
|
||||
reg = <0xff 0xffc33000 0x0 0x14>;
|
||||
clocks = <&clk CLK_PERI_APB_PCLK>;
|
||||
clock-names = "timer";
|
||||
interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
timer5: timer@ffffc33014 {
|
||||
compatible = "snps,dw-apb-timer";
|
||||
reg = <0xff 0xffc33014 0x0 0x14>;
|
||||
clocks = <&clk CLK_PERI_APB_PCLK>;
|
||||
clock-names = "timer";
|
||||
interrupts = <21 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
timer6: timer@ffffc33028 {
|
||||
compatible = "snps,dw-apb-timer";
|
||||
reg = <0xff 0xffc33028 0x0 0x14>;
|
||||
clocks = <&clk CLK_PERI_APB_PCLK>;
|
||||
clock-names = "timer";
|
||||
interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
timer7: timer@ffffc3303c {
|
||||
compatible = "snps,dw-apb-timer";
|
||||
reg = <0xff 0xffc3303c 0x0 0x14>;
|
||||
clocks = <&clk CLK_PERI_APB_PCLK>;
|
||||
clock-names = "timer";
|
||||
interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ao_gpio0: gpio@fffff41000 {
|
||||
compatible = "snps,dw-apb-gpio";
|
||||
reg = <0xff 0xfff41000 0x0 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
porte: gpio-controller@0 {
|
||||
compatible = "snps,dw-apb-gpio-port";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
ngpios = <32>;
|
||||
reg = <0>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <76 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
padctrl_aosys: pinctrl@fffff4a000 {
|
||||
compatible = "thead,th1520-pinctrl";
|
||||
reg = <0xff 0xfff4a000 0x0 0x2000>;
|
||||
clocks = <&aonsys_clk>;
|
||||
thead,pad-group = <1>;
|
||||
};
|
||||
|
||||
ao_gpio1: gpio@fffff52000 {
|
||||
compatible = "snps,dw-apb-gpio";
|
||||
reg = <0xff 0xfff52000 0x0 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
portf: gpio-controller@0 {
|
||||
compatible = "snps,dw-apb-gpio-port";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
ngpios = <32>;
|
||||
reg = <0>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <55 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -6,7 +6,7 @@ CONFIG_NR_DRAM_BANKS=1
|
||||
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000
|
||||
CONFIG_DM_GPIO=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="th1520-lichee-pi-4a"
|
||||
CONFIG_DEFAULT_DEVICE_TREE="thead/th1520-lichee-pi-4a"
|
||||
CONFIG_SPL_STACK=0xffe0170000
|
||||
CONFIG_SPL_BSS_START_ADDR=0xffe0160000
|
||||
CONFIG_SPL_BSS_MAX_SIZE=0x10000
|
||||
|
||||
Reference in New Issue
Block a user