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ARM: tegra: clock: take in account PLLD/D2 enable bit on clock_set_rate

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PLLD and PLLD2 clocks possess a unique enable bit within their
miscellaneous register. Take this into account when using clock_set_rate
function.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
This commit is contained in:
Svyatoslav Ryhel
2025-03-24 21:24:45 +02:00
parent 6bbe348bfc
commit 0edc47ba73
1 changed files with 6 additions and 0 deletions
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6
arch/arm/mach-tegra/clock.c
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@@ -703,6 +703,12 @@ int clock_set_rate(enum clock_id clkid, u32 n, u32 m, u32 p, u32 cpcon)
else
writel(base_reg, &simple_pll->pll_base);
/* PLLD and PLLD2 are only clocks which have ENABLE bit */
if (clkid == CLOCK_ID_DISPLAY)
setbits_le32(&pll->pll_misc, BIT(PLLD_CLKENABLE));
if (clkid == CLOCK_ID_DISPLAY2)
setbits_le32(&simple_pll->pll_misc, BIT(PLLD_CLKENABLE));
/*
* Changing clocks was never intended in the U-Boot for Tegra.
* If a clock is changed after clock_init() the parent rate is wrong.