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arm: dts: mediatek: update mt7981 mmc node

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1. Fix mmc clock order of mt7981 to match the clock name
2. Limit the max clock of SD to 50MHz to meet SD Card Spec 2.0
3. Increase the CLK pin driving strength to 8mA

Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
This commit is contained in:
Weijie Gao
2025-01-17 17:18:55 +08:00
committed by Tom Rini
parent 1090c6df37
commit 140303d030
2 changed files with 10 additions and 8 deletions
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6
arch/arm/dts/mt7981-sd-rfb.dts
View File

@@ -118,7 +118,7 @@
};
conf-clk {
pins = "SPI1_CS";
drive-strength = <MTK_DRIVE_6mA>;
drive-strength = <MTK_DRIVE_8mA>;
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
};
conf-rst {
@@ -140,10 +140,12 @@
};
&mmc0 {
assigned-clock-parents = <&topckgen CLK_TOP_CB_NET2_D4>,
<&topckgen CLK_TOP_CB_NET2_D2>;
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_default>;
bus-width = <4>;
max-frequency = <52000000>;
max-frequency = <50000000>;
cap-sd-highspeed;
r_smpl = <0>;
vmmc-supply = <&reg_3p3v>;

12
arch/arm/dts/mt7981.dtsi
View File

@@ -306,13 +306,13 @@
reg = <0x11230000 0x1000>,
<0x11C20000 0x1000>;
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&topckgen CLK_TOP_EMMC_400M>,
<&topckgen CLK_TOP_EMMC_208M>,
clocks = <&topckgen CLK_TOP_EMMC_208M>,
<&topckgen CLK_TOP_EMMC_400M>,
<&infracfg CLK_INFRA_MSDC_CK>;
assigned-clocks = <&topckgen CLK_TOP_EMMC_400M_SEL>,
<&topckgen CLK_TOP_EMMC_208M_SEL>;
assigned-clock-parents = <&topckgen CLK_TOP_CB_NET2_D2>,
<&topckgen CLK_TOP_CB_M_D2>;
assigned-clocks = <&topckgen CLK_TOP_EMMC_208M_SEL>,
<&topckgen CLK_TOP_EMMC_400M_SEL>;
assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D2>,
<&topckgen CLK_TOP_CB_NET2_D2>;
clock-names = "source", "hclk", "source_cg";
status = "disabled";
};